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Patent Searching and Data


Title:
LOW POWER RADIO FREQUENCY DIVIDER
Document Type and Number:
WIPO Patent Application WO/2010/022366
Kind Code:
A8
Abstract:
In accordance with the present disclosure, a multi-modulus divider (MMD) circuit configured for operation at high frequencies may include a cascade of multiple divide-by-2-or-3 cells that divides an input clock signal to produce a pulse signal. The MMD circuit may also include a pulse stretching circuit that extends the duration of the pulse signal, thereby outputting an output clock signal. The cascade of divide-by-2-or-3 cells and the pulse stretching circuit may be implemented using full-swing complementary metal-oxide-semiconductor (CMOS) circuits. Each divide-by-2-or-3 cell may be organized so that a critical path of the divide-by-2-or-3 cell comprises a first dynamic flip flop, a second dynamic flip flop, and no more than two logic stages between the first dynamic flip flop and the second dynamic flip flop.

Inventors:
ELLERSICK, William, Frederick (5775 Morehouse Drive, San Diego, CA, 92121, US)
Application Number:
US2009/054679
Publication Date:
February 25, 2010
Filing Date:
August 21, 2009
Export Citation:
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Assignee:
QUALCOMM INCORPORATED (Attn: International IP Administration, 5775 Morehouse DriveSan Diego, CA, 92121, US)
ELLERSICK, William, Frederick (5775 Morehouse Drive, San Diego, CA, 92121, US)
International Classes:
H03L7/193; H03K23/66
Attorney, Agent or Firm:
XU, Jiayu (Attn: International IP Administration, 5775 Morehouse DriveSan Diego, CA, 92121, US)
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