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Title:
LOW POWERED CLOCK DRIVING
Document Type and Number:
WIPO Patent Application WO/2022/262668
Kind Code:
A1
Abstract:
A clock driver circuit for low powered clock driving may include: a multiple phase divider; a buffer supplying at least one of multiple phases to the multiple phase divider at a center frequency that is an integer multiple of an input frequency; and wherein the multiple phase divider and the buffer share a same current from a supply rail.

Inventors:
RAMIREZ DANIEL (US)
CHAKRABORTY SUDIPTO (US)
Application Number:
PCT/CN2022/098339
Publication Date:
December 22, 2022
Filing Date:
June 13, 2022
Export Citation:
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Assignee:
IBM (US)
IBM CHINA CO LTD (CN)
International Classes:
H03L7/087; G11C11/4063
Foreign References:
US20140254295A12014-09-11
US10951216B12021-03-16
US20190102109A12019-04-04
US20180247683A12018-08-30
Attorney, Agent or Firm:
ZHONGZI LAW OFFICE (CN)
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