Title:
LOW-PROFILE MICROELECTRONIC PACKAGE, METHOD OF MANUFACTURING SAME, AND ELECTRONIC ASSEMBLY CONTAINING SAME
Document Type and Number:
WIPO Patent Application WO/2012/074783
Kind Code:
A3
Abstract:
A low-profile microelectronic package includes a die (110) (having a first surface (111) and a second surface (112)) and a package substrate (120). The substrate includes an electrically insulating layer (121) that forms a first side (126) of the substrate, an electrically conductive layer (122) connected to the die, and a protective layer (123) over the conductive layer that forms a second side (127) of the substrate. The first surface of the die is located at the first side of the substrate. The insulating layer has a plurality of pads (130) formed therein. The package further includes an array of interconnect structures (140) located at the first side of the substrate. Each interconnect structure in the array of interconnect structures has a first end (141) and a second end (142), and the first end is connected to one of the pads.
Inventors:
MANUSHAROW MATHEW J (US)
NALLA RAVI (US)
NALLA RAVI (US)
Application Number:
PCT/US2011/061338
Publication Date:
July 19, 2012
Filing Date:
November 18, 2011
Export Citation:
Assignee:
INTEL CORP (US)
MANUSHAROW MATHEW J (US)
NALLA RAVI (US)
MANUSHAROW MATHEW J (US)
NALLA RAVI (US)
International Classes:
H01L23/48; H01L23/28
Foreign References:
| US20090246909A1 | 2009-10-01 | |||
| US20030134497A1 | 2003-07-17 | |||
| US20070289127A1 | 2007-12-20 | |||
| US20090051024A1 | 2009-02-26 |
Other References:
See also references of EP 2647045A4
Attorney, Agent or Firm:
VINCENT, Lester J. et al. (1279 Oakmead ParkwaySunnyvale, California, US)
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