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Title:
LOW-TEMPERATURE PASSIVATION OF FERROELECTRIC INTEGRATED CIRCUITS FOR ENHANCED POLARIZATION PERFORMANCE
Document Type and Number:
WIPO Patent Application WO/2016/049084
Kind Code:
A1
Abstract:
Curing of a passivation layer (60) is applied to the surface of a ferroelectric integrated circuit to enhance the polarization characteristics of ferroelectric structures (55). A passivation layer (60), such as a polyimide, is applied to the surface of the ferroelectric integrated circuit after fabrication of the active devices. The passivation layer (60) is cured by exposure to a high temperature, below the Curie temperature of ferroelectric material (62), for a short duration such as on the order of ten minutes. Variable frequency microwave energy may be used to effect such curing. The cured passivation layer (60) attains a tensile stress state, and as a result imparts a compressive stress upon the underlying ferroelectric material (62). Polarization may be further enhanced by polarizing the ferroelectric material (62) before the cure process.

Inventors:
WEN, Huang-Chun (4016 Rawlins Street, Dallas, TX, 75219, US)
BAILEY, Richard, Allen (1906 Trailridge Drive, Richardson, TX, 75081, US)
ACOSTA, Antonio, Guillermo (1909 Duke Drive, Richardson, TX, 75081, US)
RODRIGUEZ, John, A. (5009 Harvest Hill Road, Dallas, TX, 75244, US)
SUMMERFELT, Scott, Robert (3202 Bridle Path Court, Garland, TX, 75044, US)
SAN, Kemal, Tamer (1416 Harrington Drive, Plano, TX, 75075, US)
Application Number:
US2015/051552
Publication Date:
March 31, 2016
Filing Date:
September 22, 2015
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
TEXAS INSTRUMENTS INCORPORATED (P.O. Box 655474, Mail Station 3999Dallas, TX, 75265-5474, US)
TEXAS INSTRUMENTS JAPAN LIMITED (24-1, Nishi-Shinjuku 6-chomeShinjuku-ku, Tokyo, 160-8366, JP)
International Classes:
H01L27/115; H01G7/06
Foreign References:
US4149302A1979-04-17
US20140147940A12014-05-29
US5525528A1996-06-11
US5795794A1998-08-18
US20090155931A12009-06-18
US20130078742A12013-03-28
Attorney, Agent or Firm:
DAVIS, Jr., Michael, A. et al. (Texas Instruments Incorporated, P.O. Box 655474 Mail Station 399, Dallas TX, 75265-5474, US)
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Claims:
CLAIMS

What is claimed is:

1. A method of manufacturing an integrated circuit, the method comprising:

forming at least one circuit element including a layer of a ferroelectric material near a semiconducting surface of a body;

then forming at least one level of conductors overlying the element, each level including patterned metal conductors and a dielectric layer;

forming a protective overcoat layer over the surface and overlying the at least one circuit element and the at least one level of conductors;

then depositing a passivation layer over the protective overcoat layer; and

heating the passivation layer to a temperature below a Curie temperature of the ferroelectric material for a duration sufficient to cure the material of the passivation layer into a tensile stress state, and of less than approximately twenty minutes.

2. The method of claim 1, wherein the ferroelectric material is lead-zirconium-titanate.

3. The method of claim 2, wherein the heating step heats the passivation layer to a curing temperature at or below approximately 390°C.

4. The method of claim 1, wherein the at least one circuit element includes a plurality of ferroelectric capacitors, and further comprising: before the heating step, polarizing the ferroelectric capacitors.

5. The method of claim 4, wherein the at least one circuit element further includes a plurality of metal-oxide-semiconductor (MOS) transistors, each associated with one of the ferroelectric capacitors in a plurality of memory cells; wherein each of the plurality of ferroelectric capacitors includes first and second parallel conductive plates disposed on either side of the ferroelectric material, the first plate coupled to a plate line conductor in the integrated circuit, and the second plate coupled to a source/drain region of its associated MOS transistor; and wherein the polarizing step includes: applying a voltage at or above a coercive voltage across each of the ferroelectric capacitors, at a positive polarity at the first plate relative to the second plate.

6. The method of claim 1, wherein the passivation layer includes a polymer-containing soft stress release material having a low elastic modulus as compared with Si02.

7. The method of claim 6, wherein the polymer-containing soft stress release material is selected from the group consisting of polyimides, polybenzoxazole (PBO), benzocyclobutene- based polymers (BCB), and fluoro-polymers.

8. The method of claim 1, wherein the passivation layer includes a polyimide, and wherein the heating step includes: exposing the passivation layer to variable frequency microwave energy.

9. The method of claim 1 , wherein the heating step heats the passivation layer from an ambient temperature to a curing temperature of at least 340°C and below the Curie temperature of the ferroelectric material at a ramp rate of at least 0.40°C per second.

10. The method of claim 1, wherein the heating step maintains the passivation layer at the curing temperature for a maximum duration of approximately ten minutes.

11. The method of claim 1, wherein after the exposing step, the passivation layer cools from the curing temperature at a ramp rate of at least approximately 0.40°C per second.

12. The method of claim 1, wherein the step of forming at least one level of conductors includes: depositing a barrier layer including silicon nitride; then depositing a metallization layer including copper; and then removing selected portions of the metallization layer to define the conductors.

13. An integrated circuit, comprising:

at least one circuit element including a layer of a ferroelectric material, and disposed near a semiconducting surface of a body;

at least one layer of insulating material disposed over the surface and overlying the at least one circuit element;

at least one level of conductors disposed near the surface;

a protective overcoat layer, including an insulating material, disposed over the ferroelectric circuit element, the at least one layer of insulating material, and the at least one level of conductors; and

a passivation layer overlying the protective overcoat layer, the passivation layer having a tensile stress state, and formed by a process including: heating the passivation layer to a temperature below a Curie temperature of the ferroelectric material for a duration sufficient to cure the material of the passivation layer into a tensile stress state, and of less than approximately twenty minutes.

14. The integrated circuit of claim 13, further comprising: a plurality of solder balls near the surface, in contact with conductors through openings in the passivation layer.

15. The integrated circuit of claim 13, wherein the passivation layer includes a polymer-containing soft stress release material having a low elastic modulus as compared with Si02.

16. The integrated circuit of claim 15, wherein the polymer-containing soft stress release material is selected from the group consisting of polyimides, polybenzoxazole (PBO), benzocyclobutene-based polymers (BCB), and fluoro-polymers.

17. The integrated circuit of claim 13, wherein the at least one circuit element includes a plurality of ferroelectric capacitors, each including first and second parallel conductive plates disposed on either side of the ferroelectric material.

18. The integrated circuit of claim 17, wherein the at least one circuit element further includes a plurality of metal-oxide-semiconductor (MOS) transistors, each associated with one of the ferroelectric capacitors in a plurality of memory cells; and wherein each of the plurality of ferroelectric capacitors includes first and second parallel conductive plates disposed on either side of the ferroelectric material, the first plate coupled to a plate line conductor in the integrated circuit, and the second plate coupled to a source/drain region of its associated MOS transistor.

19. A method of manufacturing an integrated circuit, the method comprising:

forming at least one circuit element including a layer of a ferroelectric material near a semiconducting surface of a body;

then forming at least one level of conductors overlying the element, each level including patterned metal conductors and a dielectric layer;

forming a protective overcoat layer over the surface and overlying the at least one circuit element and the at least one level of conductors;

then depositing a passivation layer of a material including a polymer-containing film over the protective overcoat layer; and

applying electromagnetic energy to the passivation layer at a frequency corresponding to a vibrational frequency of the polymer, to heat the passivation layer to a temperature below a Curie temperature of the ferroelectric material for a duration sufficient to cure the material of the passivation layer into a tensile stress state.

20. The method of claim 19, wherein the step of applying electromagnetic energy to the passivation layer is performed for a duration of less than approximately twenty minutes.

Description:
LOW-TEMPERATURE PASSIVATION OF FERROELECTRIC INTEGRATED CIRCUITS FOR ENHANCED POLARIZATION PERFORMANCE

BACKGROUND

[0001] This relates generally to integrated circuit manufacture, and more particularly to the formation of capacitors in memory devices, such as ferroelectric memories.

[0002] A recently developed technology for realizing non-volatile solid-state memory devices involves the construction of capacitors in which the dielectric material is a polarizable ferroelectric material, such as lead-zirconium-titanate (PZT) or strontium-bismuth-tantalate (SBT), rather than silicon dioxide or silicon nitride as typically used in non-ferroelectric capacitors. Hysteresis in the charge-versus-voltage (Q-V) characteristic of the ferroelectric material, based on its polarization state, enables the non- volatile storage of binary states in those capacitors. In contrast, conventional MOS capacitors lose their stored charge on power-down of the device.

[0003] Non-volatile solid-state read/write random access memory (RAM) devices based on ferroelectric capacitors (such memory devices commonly referred to as "ferroelectric RAM", "FeRAM" or "FRAM" devices) have been implemented in many electronic systems, particularly portable electronic devices and systems. FRAMs are especially attractive in implantable medical devices, such as pacemakers and defibrillators. Various memory cell architectures including ferroelectric capacitors are known, such as the well-known 1T1C (one transistor, one capacitor) and 2T2C (two transistor, two capacitor) cells, among others. Ferroelectric capacitors are also implemented in some integrated circuits as programmable analog capacitors.

[0004] FIG. la illustrates the construction of an example of a portion of an integrated circuit including conventional 1T1C ferroelectric random access memory (FRAM) cell 6. In this example, cell 6 includes ferroelectric capacitor 2 and metal-oxide-semiconductor (MOS) transistor 5, where one plate of capacitor 2 is connected to one end of the source/drain path of transistor 5. Capacitor 2 and transistor 5 are both disposed at or near a semiconducting surface of a semiconductor substrate. Alternatively, capacitor 2 and transistor 5 may instead be formed at the surface of a semiconductor layer that overlies an insulator layer, such as by conventional silicon-on-insulator (SOI) technology. In the example of FIG. la, n-channel MOS transistor 5 includes n-type source/drain regions 14 at the surface of p-type substrate 10 (or of a p-type "well" formed into substrate 10), with gate electrode 16 overlying a channel region between source/drain regions 14, and separated from that channel region by gate dielectric 17. Isolation dielectric structures 15 are disposed at or near the surface of substrate 10 to isolate transistors from one another, in a conventional manner for MOS integrated circuits. Interlevel dielectric 13 is disposed over transistor 5, with conductive plug 18 disposed in a contact opening through interlevel dielectric 13 to provide a conductive connection between one of source/drain regions 14 of transistor 5 and lower plate 20a of ferroelectric capacitor 2. Gate electrode 16 corresponds to the word line of cell 6, while the one of source/drain regions 14 (not in contact with conductive plug 18) corresponds to the bit line of the column in which cell 6 resides.

[0005] In the example of FIG. la, ferroelectric capacitor 2 is formed of a ferroelectric "sandwich" stack of conductive plates 20a, 20b, between which ferroelectric material 22 is disposed. Lower conductive plate 20a is formed at a location overlying conductive plug 18, to be in electrical contact with the underlying source/drain region 14 of transistor 5 by that conductive plug 18. Upper conductive plate 20b will receive a plate line voltage during operation of cell 6, as described below. Lower conductive plate 20a and upper plate 20b are formed from one or more layers of conductive metals, metal oxides, and other materials. In a typical construction of lower conductive plate 20a, a stack of a diffusion barrier layer is in contact with conductive plug 18, and a layer of a noble metal (e.g., Ru, Pt, Ir, Rh, Pt, Pd, Au) or metal oxide (e.g., RuOx, IrOx, PdOx, SrRu0 3 ) is overlying the barrier layer and in contact with the ferroelectric material 22. Conductive plates 20a, 20b are typically formed of the same conductive material or materials as one another, for purposes of symmetry, simplicity of the manufacturing flow, and improved ferroelectric polarization performance. As mentioned above, ferroelectric material 22 in capacitor 2 is typically lead-zirconium-titanate (PZT) or strontium-bismuth-tantalate (SBT), either of which may be deposited by metalorganic chemical vapor deposition. Ferroelectric material 22 is desirably as thin as practicable, for purposes of electrical performance (e.g., polarization), and for consistency with the deep sub-micron features that are used in modern integrated circuits.

[0006] FIG. lb illustrates an example of a Q-V characteristic of a conventional ferroelectric capacitor, such as capacitor 2 of FIG. la. As shown, the charge (Q) stored across the conductive plates depends on both the voltage currently applied to the plates (V) and the recent history of that voltage. In this example, capacitor 2 is polarized into the state by application of a voltage V exceeding a "coercive" voltage +V a across the capacitor plates (conductive plates 20a, 20b). After being polarized to the state, capacitor 2 will exhibit a stored charge of +Qi, so long as voltage V remains above coercive voltage -Vp. Conversely, if the voltage V applied across the capacitor plates is more negative than coercive voltage -Vp, then capacitor 2 is polarized into the state and will exhibit a stored charge of -Q 2 for an applied voltage V below +V a .

[0007] For purposes of non-volatile storage in integrated circuits, an important characteristic of ferroelectric capacitors is the difference in capacitances exhibited by a ferroelectric capacitor in its respective polarized states. Fundamentally, capacitance is the ratio of stored charge to applied voltage. Ferroelectric capacitors exhibit a linear capacitance by virtue of their parallel plate construction, and also a significant polarization capacitance by virtue of their response to changes in polarization state upon application of a polarizing voltage. For example, referring to FIG. lb, the polarization of a ferroelectric capacitor from its state to its state by an applied voltage above coercive voltage V a is reflected by a relatively high capacitance C(-l) corresponding to the polarization charge stored in the capacitor due to its change of polarization state. The differential charge stored as a result of the polarization of the capacitor from one state to the opposite state is commonly referred to as the "switching polarization". If a capacitor is already in its state, then it exhibits little capacitance C(+l) from re-polarization to the state, because its ferroelectric domains are already aligned in the direction of the applied coercive voltage, so little additional polarization charge is stored. Accordingly, the polarization state of a ferroelectric memory cell (i.e., the stored data state) is conventionally read by application of a coercive voltage to the ferroelectric capacitor and sensing the exhibited capacitance.

[0008] FIGS, lc and Id illustrate a read operation of an instance of FRAM cell 6 jk , which resides in column j and row k of an FRAM memory array. In this conventional approach, a read is performed by applying a low voltage V ss to bit line BL k , then isolating bit line BL k to leave it floating, and then raising the voltage of plate line PL from the low voltage V ss to a high voltage V cc above the coercive voltage +V a of capacitor 2 while word line WL j is energized to turn on transistor 5. The high plate line voltage interrogates the polarization capacitance of capacitor 2 according to the hysteresis diagram of FIG. la, producing a read current i R through transistor 5 to bit line BL k . Sense amplifier 8, coupled to bit line BL k , senses the voltage V BL established at the capacitance BLC (which is typically parasitic) of bit line BL k by read current 1 R to discern the stored data state. As shown in FIG. Id, if capacitor 2 of cell 6 jk was previously in the polarization state, the relatively low read current 1 R will establish a relatively low level (< V REF ) voltage transition V(0) that will be interpreted by sense amplifier 8 as a "0" data state. Conversely, if capacitor 2 of cell 6 jk was previously in the polarization state, the stronger read current 1 R will establish a relatively high level (> V REF ) voltage transition V(l) that will be interpreted by sense amplifier 8 as a "1" data state. The "read margin" of cell 6 jk corresponds to the difference in the levels of read current i R , and the corresponding difference in bit line voltage V BL relative to reference voltage V REF , established by the two polarization states of capacitor 2 in cell 6jk.

[0009] Ferroelectric capacitors (and thus memories incorporating such devices) are vulnerable over time to weakening of the switching polarization, commonly referred to as "aging". This weakening corresponds to collapse of the polarization hysteresis loop, such as shown by curves 3+, 3- of FIG. lb. In the memory context, this weakened switching polarization will appear as a loss of read margin and a corresponding increased likelihood of read errors.

[0010] Exposure of ferroelectric integrated circuits to high temperatures, such as those encountered in manufacturing processes following the deposition of the ferroelectric material, can degrade the polarization characteristics of that material. Examples of such high temperature processes include those involved in forming metal conductor levels in the integrated circuit itself, packaging of the integrated circuit (e.g., thermal curing of plastic mold compound), assembling the packaged device into its system application (e.g., solder reflow), and operating the device at elevated temperatures. Extended or repeated exposure to temperature will degrade the ability of the material to fully repolarize, typically due to hydrogen diffusing into the ferroelectric material. Accordingly, it is useful to minimize exposure of the integrated circuit to high temperatures subsequent to ferroelectric deposition.

[0011] Packaging of the integrated circuit can also result in mechanical stresses applied to the surface of the die, with such stresses being sufficient in some cases to cause cracking of the protective overcoat film at the die or even displacement of metal conductors or other features to cause device failure. These stresses can be especially severe in the case of packages of the type in which a cured plastic mold compound encapsulates the integrated circuit die. Various approaches for reducing the mechanical stresses caused by packaging are known. One approach is the application of a stress relief layer, such as an organic film or coating, to the surface of the integrated circuit die before molding. The use of a polyimide film as this stress relief layer is widespread, due to its compatibility with photolithographic patterning and etching to expose the bond pads of the die and its other favorable thermal and mechanical properties. According to conventional processing techniques, the formation of the polyimide film involves a final bake process to cure the material. This final bake is typically performed at an elevated temperature for a significant duration, such as 375°C for one hour. However, as discussed above, thermal processes following the fabrication of ferroelectric elements, such as ferroelectric capacitors, tend to degrade the switching polarization characteristics of the material and thus such performance parameters as read margin in FRAM applications. Accordingly, the conventional bake used to cure the polyimide stress relief film tends to degrade the ferroelectric material. Use of the polyimide stress relief film as applied in a conventional manner is thus discouraged for ferroelectric integrated circuits.

[0012] The packaging of integrated circuits into die-size packages (referred to as wafer-chip- scale packages ("WCSP")) has become popular. According to this approach (such as described in U.S. Patent Application Publication No. US 2012/0211884 Al, published August 23, 2012, commonly assigned herewith and incorporated herein by this reference), the WCSP eliminates encapsulation of the integrated circuit die with mold compound, instead forming solder balls or "bumps" onto conductive pads at the surface of the integrated circuit. Passivation layers, typically formed of a polyimide, are formed over the integrated circuit to define the locations of the conductive pads, and in some cases to also insulate an additional patterned conductive layer (i.e., a redistribution layer, or "RDL") that routes signals from the solder balls to the bond pads of the integrated circuit die. A WCSP is mounted to a printed circuit board by placing it upside-down, with the solder balls at corresponding lands on the circuit board. A solder ref ow will then attach the package to the printed circuit board via the reflowed solder balls.

[0013] As discussed above, a conventional polyimide cure processes involved in WCSP technology will degrade the switching polarization characteristics of ferroelectric material, especially if multiple passivation layers are necessary because an RDL is required. This degradation in polarization, and in read margin in the FRAM context, can be sufficiently severe that the device cannot tolerate the additional degradation from the subsequent solder reflow process. Accordingly, WCSP technology has not been available for integrated circuits, such as FRAMs, that include ferroelectric structures.

[0014] U.S. Patent No. 8,778,774, which is incorporated herein by this reference, describes the application of external mechanical stress to a semiconductor wafer to increase the polarization of ferroelectric devices in integrated circuits on that wafer.

SUMMARY

[0015] In described examples of a method of fabricating a ferroelectric integrated circuit, and in described examples of the integrated circuit so fabricated, the polarization characteristics of the ferroelectric material are enhanced.

[0016] Such integrated circuit can tolerate subsequent thermal processes.

[0017] Also, such a method and integrated circuit provide improved read margin for ferroelectric memories.

[0018] In such a method and integrated circuit, the polarization characteristics are enhanced without requiring modification of processes involved in forming the ferroelectric structure.

[0019] Such a method and integrated circuit can be packaged by wafer-chip-scale package (WCSP) technology.

[0020] According to some described examples, a passivation material is applied to the surface of a ferroelectric integrated circuit die, and is cured to a tensile stress state that imparts compressive stress to the underlying ferroelectric material. In one example, the passivation material is a polyimide film that is cured by a thermal process with fast temperature ramp that heats the film to a temperature below the Curie temperature of the ferroelectric material for a short time period.

BRIEF DESCRIPTION OF THE DRAWINGS

[0021] FIG. la is a cross-sectional view of a portion of an integrated circuit, including a ferroelectric capacitor constructed according to conventional methods.

[0022] FIG. lb is a plot of a charge-versus-voltage characteristic of a conventional ferroelectric capacitor.

[0023] FIG. lc is an electrical diagram, in schematic and block form, of a conventional 1T-1C ferroelectric memory cell.

[0024] FIG. Id is a timing diagram of the operation of a read of the 1T-1C ferroelectric memory cell of FIG. lc.

[0025] FIG. 2 is a flow diagram of the process flow for manufacturing a ferroelectric integrated circuit according to an embodiment.

[0026] FIG. 3 is a cross-sectional view, in schematic form, of a portion of an integrated circuit fabricated according to the embodiment of FIG. 2, and illustrating the effect of an overlying passivation film on a ferroelectric structure.

[0027] FIG. 4 is a cross-sectional view, in schematic form, of a portion of an integrated circuit fabricated according to the embodiment of FIG. 2 as packaged in a wafer-chip-scale package. DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

[0028] The one or more embodiments described in this specification are implemented into integrated circuits with ferroelectric memories, such as ferroelectric random access memories (FRAMs). Such implementation is particularly advantageous in that context. However, these concepts may be beneficially applied to in other applications, such as integrated circuits with other types of ferroelectric structures and devices.

[0029] Cured polyimide adheres well to the surface of an integrated circuit, and that such adhesion is important in the ability of the polyimide film to serve as a stress relief agent for the integrated circuit when packaged, such as in a molded plastic package. However, as mentioned above, the application of a stress relief film of polyimide or other materials that require curing or anneal is strongly discouraged for integrated circuits that include ferroelectric devices, because the time and temperature required for curing the stress relief film significantly degrade the polarization characteristics of the ferroelectric material. In a specific example, the typical curing process for a polyimide stress relief film is a bake at 375°C for on the order of one hour, which is essentially fatal to the polarization characteristics of lead-zirconium-titanate (PZT) ferroelectric material. It is believed that this degradation results from the diffusion of hydrogen into the ferroelectric film, such diffusion being accelerated by the time and temperature required to cure polyimide in a conventional manner. Accordingly, conventional ferroelectric devices are typically packaged without use of a polyimide stress relief film. This inability to use polyimide with ferroelectric integrated circuits essentially renders impossible the use of wafer-chip-scale package (WCSP) technology for ferroelectric devices, because one or more polyimide passivation films are necessary to form the solder balls and redistribution conductor layers in such packages. [0030] However, polyimide film, when cured, exhibits an intrinsic tensile stress. Also, because of the excellent adhesion of cured polyimide to the surface of an integrated circuit, the intrinsic tensile stress in the cured polyimide film exerts a compressive stress on thin film layers in the underlying integrated circuit to such an extent that the polarization characteristics of the ferroelectric material are enhanced. According to example embodiments, an approach has been discovered for curing a passivation film (e.g., polyimide) at the surface of a ferroelectric integrated circuit, such that the intrinsic tensile stress in the cured passivation film imparts beneficial compressive stress in underlying ferroelectric material, without degrading the polarization of that ferroelectric material due to hydrogen diffusion or other time-and- temperature polarization degradation mechanisms. Embodiments incorporating this discovery will now be described in detail.

[0031] FIG. 2 illustrates a process flow, according to certain embodiments, for fabricating an integrated circuit with ferroelectric circuit elements, such as ferroelectric capacitors in the form described above relative to FIGS, la through Id, such that the polarization characteristics of the ferroelectric material are enhanced. This process flow begins with process 30, in which transistors (such as transistor 5 of FIG. la) are formed at or near the semiconducting surface of a substrate or other support body in a conventional manner. In particular, the substrate may correspond to single-crystal silicon with the appropriate dopant concentration, along with such structures as isolation dielectric structures and the appropriate doped wells as desired. Alternatively, in the silicon-on-insulator context, the substrate may correspond to a "handle" wafer on which an insulating layer is formed, with the transistors and other circuit elements formed in an overlying epitaxial silicon layer. In either case, structures and features (such as a gate dielectric layer, gate electrodes and source/drain regions) are formed at or near the surface of the substrate according to conventional MOS processes. In the CMOS context, these transistors may include both p-channel MOS and n-channel MOS transistors. Other circuit elements (such as MOS capacitors and resistors) may also be fabricated in this process 30, with interlevel dielectric layers formed and contact openings formed through such layers as appropriate for the particular circuit layout.

[0032] After process 30 in the process flow of FIG. 2, a ferroelectric capacitor (such as capacitor 2 of FIG. la) is then formed, beginning with process 32 in which one or more conductive layers are formed to serve as the lower conductive plate layer. Typically, process 32 will be performed by sputter deposition of one or more layers of the desired conductive material, such as one or more of strontium ruthenate (SrRu0 3 ), iridium (Ir), iridium oxide (Ir0 2 ), platinum (Pt), and other metals and metal oxides suitable for use in this application, along with the appropriate barrier metal layers disposed between the lower conductive plate layer and underlying structures. In many implementations, the particular conductors deposited in process 32 are selected for compatibility with the ferroelectric material to be deposited over this layer, and with the temperatures and other conditions that the structure will be exposed to in the remainder of the manufacturing process. After the deposition of the lower conductive plate layer in process 32, ferroelectric material such as lead-zirconium-titanate (PZT) is deposited overall by metalorganic chemical vapor deposition in process 34. Examples of deposition processes suitable for use in process 34 according to this embodiment are described in U.S. Patents No. 6,730,354 and No. 8,962,350, both commonly assigned herewith and incorporated herein by reference. Upon completion of PZT deposition process 34, an upper conductive plate layer is then deposited over the ferroelectric material in process 36, such as by sputter deposition. The composition of this upper conductive plate layer will typically be the same as that of lower conductive plate layer, for symmetry and to allow the use of the same materials and processes for each. If lower and upper conductive plate layers are composed of a stack of multiple conductive materials, the order of deposition of those materials in the upper plate layer will typically be reversed from that for the lower plate layer. In process 38, the ferroelectric capacitor is then completed by photolithographic patterning of photoresist or another mask layer to define its size and location, followed by a single masked stack etch of the upper and lower conductive plate layers and the ferroelectric material between those layers. Commonly assigned U.S. Patent No. 6,656,748, incorporated herein by reference, describes an example of ferroelectric stack formation and etch that is suitable for use as process 38 in connection with embodiments. Also, in process 38, a ferroelectric passivation film may optionally be formed over the etched capacitor structure, such as described in U.S. Patent Publication No. 2013/0056811, published March 7, 2013, commonly assigned herewith and incorporated herein by this reference.

[0033] In process 40, conventional processes for forming one or more levels of metal conductors are then performed to define interconnections among the various circuit elements in the integrated circuit being formed. Typically, process 40 for a given level of interconnection will include the deposition of a interlevel dielectric layer, a patterned etch of that interlevel dielectric layer to form vias and contacts to underlying conductors, deposition of conductive material including at least a layer of a metal conductor and perhaps conductive plugs to fill vias through the interlevel dielectric, and a patterned etch of the metal layer to define the routing of the metal conductors in that level. Process 40 is repeated as desired to form additional conductor levels. Integrated circuits with six or seven metal levels are common.

[0034] The particular material of the metal layer or layers deposited and patterned in process 40 may be aluminum, copper, other conventional metals, or alloys and other combinations of these metals. Copper metallization typically requires the use of an underlying barrier layer, typically silicon nitride, to limit the diffusion of copper into the underlying transistors. However, silicon nitride tends to contain a relatively high concentration of hydrogen, which may diffuse into and thus degrade the ferroelectric material as a result of subsequent thermal processes. Aluminum metallization typically contains less hydrogen, and is thus believed to be more compatible with ferroelectric integrated circuits. But as will become apparent from this description, the described embodiments enable the use of copper metallization even with a silicon nitride barrier layer, while avoiding degradation in the polarization characteristics of the ferroelectric material.

[0035] After process 40, a protective overcoat layer (typically composed of silicon nitride or silicon oxynitride) is deposited overall in process 42. In process 44, photolithographic patterning and etching of the protective overcoat is then performed to form openings over the bond pads in the upper metal level, in a conventional manner.

[0036] According to this embodiment, a passivation film is then deposited over the surface of the integrated circuit in process 46. The composition of this passivation film is of a material that attains a stress state when cured in the manner to be described below according to this embodiment, such that the stress state of the cured passivation film exerts a stress on the underlying ferroelectric circuit elements in the integrated circuit. An example of such a passivation film is a polyimide, such as the HD4100 polyimide product available from HD Micro Systems. Other materials suitable for use as the passivation film include polybenzoxazole (PBO), benzocyclobutene -based polymers (BCB), fluoro-polymers, and other polymer-containing soft stress release materials having a low elastic modulus as compared with Si0 2 . Process 46 may be performed in a conventional manner for the selected passivation film material, such as by spinning on or otherwise dispensing the passivation film material onto the surface of the wafer, to a thickness on the order of several micrometers. An example of a passivation film dispensed in process 44 according to this embodiment is a 10 μιη layer of the HD4100 polyimide.

[0037] In process 47, selected locations of the passivation film deposited in process 44 is photolithographically removed to expose the bond pads previously exposed by the etch of the underlying protective overcoat in process 42. If the passivation film is a photosensitive polyimide or similar film, the bond pad openings and other selected locations of the film will be removed in process 47 by masked exposure and developing of the film as appropriate for the particular material. If the passivation film requires chemical etching, process 47 will involve conventional photolithographic pattern and etch processes. According to this alternative, the previous protective overcoat etch of process 42 may in some cases be omitted from the process flow, with process 47 then including both an etch of the passivation film and an etch of the underlying protective overcoat to expose the bond pads in the upper metal level.

[0038] Process 48 is then performed to cure the passivation film deposited in process 44. Generally, cure process 48 is performed by heating the wafer including the integrated circuit being fabricated, with the passivation film deposited in process 44, to a selected cure temperature for a selected time duration at that cure temperature. According to these embodiments, the time and temperature conditions of cure process 48 are selected to cure the passivation film into a state, in which it exhibits an intrinsic tensile stress sufficient to impart a compressive stress in underlying ferroelectric material, without degrading the polarization of that ferroelectric material due to hydrogen diffusion or other time-and-temperature polarization degradation mechanisms. The range of conditions of cure process 48 will depend, at least in part, on the specific materials used for the ferroelectric material and the passivation film.

[0039] However, certain general limits for the time and temperature conditions of cure process 48 have been discovered in connection with these embodiments. Ferroelectric material exhibits a "Curie temperature", which is defined as the temperature at which, absent an externally applied electric field, the crystal structure of the ferroelectric material undergoes a phase change that causes loss of polarization. While the depolarized material will repolarize on application of a coercive voltage, it is believed that repeated or extended exposure of the ferroelectric material to temperatures above the Curie temperature will result in some permanent degradation in its polarization characteristics. Accordingly, cure process 48 in this embodiment is carried out at a cure temperature below the Curie temperature of the ferroelectric material deposited in process 34. This cure temperature is contemplated to be the temperature measured at the wafer, such as by a non-contact IR pyrometer.

[0040] Secondly, as noted above, the duration of high temperature exposure of the ferroelectric material is a significant factor in the degradation of its polarization characteristics. Accordingly, cure process 48 in this embodiment is performed by minimizing the time at which the cure temperature is maintained, and by maximizing the ramp rate at which the wafer is heated to the cure temperature and then cooled from the cure temperature, to minimize the overall exposure of the ferroelectric material to high temperatures in cure process 48.

[0041] An example of cure process 48 that has been observed, by experiment, to enhance the polarization characteristics of PZT ferroelectric material, is carried out by electromagnetic heating. In this embodiment, the electromagnetic heating of process 48 involves the application of electromagnetic energy to the passivation film at a frequency that couples to the vibrational frequency of the polymer of the passivation film, which heats and cures the film. One type of electromagnetic heating that has been observed to be suitable for cure process 48 is microwave heating, such as may be applied by a variable frequency microwave system in which the frequency of the electromagnetic wave can be selected (e.g., over a range from ~5 GHz to ~9 GHz) to efficiently couple to the polymer of the particular passivation film. As known (such as described in U.S. Patent No. 7,939,456, incorporated herein by reference), variable frequency microwave heating is typically performed by selecting a center frequency for the microwave energy, and then rapidly and substantially continuously sweeping the frequency over a frequency range around that center frequency, such as over a range of ±5% around the center frequency, although this range may vary based on the particular equipment used. In this example of cure process 48, the wafer or wafers including integrated circuits with ferroelectric circuit elements fabricated as described above, including a passivation film of HD4100 polyimide at a thickness of ~10 μιη, are placed into the vacuum chamber of a variable frequency microwave system and heated by the application of microwave energy at a center frequency of -6.25 GHz, modulated over a range of approximately ±6.25%_(0.4 GHz). This variable frequency microwave energy heats the wafer to a cure temperature, measured at the wafer, of at least ~340°C and at or below ~390°C (400°C being the Curie temperature of the deposited PZT in this example), such as ~360°C, for less than twenty minutes, and such as for approximately five to ten minutes. [0042] The use of electromagnetic heating to carry out cure process 48 is contemplated to be especially beneficial in connection with these embodiments, considering that the electromagnetic energy can couple to the organic molecules of the polyimide passivation film (and similarly to other organic materials as used for the passivation film) much more strongly than it can to the inorganic molecules of the underlying integrated circuit, including the ferroelectric material. Accordingly, this difference in coupling efficiently heats the passivation film to carry out the curing mechanism, while minimizing the energy delivered to the ferroelectric material. Accordingly, the use of electromagnetic heating operates to control the thermal exposure of the device in cure process 48, but does not directly impact the performance of the ferroelectric material. In fact, the only heating of the ferroelectric material caused by electromagnetic curing used in process 48 will be heat conducted from the passivation film to the ferroelectric material through the intervening layers therebetween. Accordingly, the electromagnetic heating of the passivation film is well-suited to curing that film in the minimum time, to minimize temperature exposure of the underlying ferroelectric material.

[0043] Variable frequency microwave is believed to be a particularly useful type of electromagnetic heating for use in curing process 48. For example, as described in the above-incorporated U.S. Patent No. 7,939,456, variable frequency microwave heating in the processing of semiconductor wafers avoids damaging arc formation, and also provides more uniform heating over the wafer. This more uniform heating provided by variable frequency microwave energy is believed to significantly improve the curing of the passivation film in process 48 in this embodiment, enabling shorter cure times and thus reducing the degradation of the underlying ferroelectric material by exposure to the elevated curing temperature.

[0044] The heating of the wafer from ambient temperature to the cure temperature, as measured by a non-contact IR pyrometer directed at the wafer surface (i.e., the polyimide passivation film), is carried out in this example at a ramp rate of at least 0.40°C per second, such as 0.60°C per second. The ramp rate at which the wafer returns to the ambient temperature from the cure temperature should also be maximized, in this embodiment, with a desirable ramp rate being at least 0.40°C per second, such as 0.60°C per second. Heating and cooling ramp rates resembling a "step function" would be desirable, to the extent attainable in physical systems, considering that the extent of the curing mechanism from the temperatures below the eventual cure temperature are expected to be insignificant, while the degrading effects on the ferroelectric material of the temperature exposure in those ramp periods will be cumulative. In this regard, use of a smaller capacity variable frequency microwave system (such as a single-wafer system) in curing process 48 may further reduce degradation of the ferroelectric material, because such smaller systems will tend to have shorter cool-down times than larger batch systems.

[0045] Other approaches to curing the passivation film in process 48 may alternatively be used. For example, rapid thermal anneal (RTA) may be a suitable technology for cure process 48. In this regard, relatively simple modifications to the configuration of conventional RTA systems will enable their use in cure process 48 according to these embodiments. In other approaches to cure process 48, the time at the cure temperature is limited, while sufficiently curing the passivation film.

[0046] FIG. 3 schematically illustrates the result of passivation film deposition process 44 and cure process 48 on the underlying ferroelectric structures. In this example, ferroelectric capacitor 55 has been formed at or near the surface of substrate 52, and includes lower and upper plates 60a, 60b on either side of ferroelectric material 62. Dielectric material 54 is disposed over and around lower and upper plates 60a, 60b and ferroelectric material 62, and includes the various interlevel dielectric layers that insulate the metal levels (not shown) in the integrated circuit, and the protective overcoat layer deposited in process 42. In this schematic view of FIG. 3, polyimide passivation film 60 is disposed over dielectric material 54.

[0047] As evident by the force arrows shown in FIG. 3, upon curing of polyimide passivation film 60 in cure process 48 according to these embodiments, passivation film 60 exhibits an intrinsic tensile stress. Because of the excellent adhesion of polyimide passivation film 60 to the surface of dielectric material 54, as is typical in conventional integrated circuits, this tensile stress state of passivation film 60 imparts a compressive stress on the underlying dielectric material 54. This compressive stress on dielectric material 54 will be transferred also to ferroelectric material 62, as evident by the force arrow shown in FIG. 3 for that layer. This compressive stress has been observed to improve the polarization performance of ferroelectric material 62.

[0048] Referring back to FIG. 2, programming process 45 may optionally be performed before cure process 48. For example, as shown in FIG. 2, programming process 47 is performed after access to the bond pads or other terminals of the integrated circuit is provided by the patterned etch of the protective overcoat in process 46, before deposition of the passivation film. It has been observed, in connection with some embodiments, that the enhancement in the polarization characteristics of ferroelectric circuit elements resulting from the compressive stress imparted to the ferroelectric material by the cured passivation film (as discussed above relative to FIG. 3) is further enhanced in those cases in which the ferroelectric material is programmed (i.e., polarized) before cure process 48. Accordingly, programming process 47 is performed by the application of a voltage to each of the ferroelectric structures in the integrated circuit that is at or above the coercive voltage for those ferroelectric structures. Typically, this programming process 47 will be performed using conventional automated test equipment, such as at the time that the wafer containing the integrated circuits is electrically tested after its fabrication (e.g., at any time after protective overcoat process 42 and before cure process 48).

[0049] It has also been observed, in connection with some of these embodiments, that the polarity of the polarization applied in programming process 47 can affect the enhancement effect of the applied compressive stress on the ferroelectric material. For the example of ferroelectric capacitors that are electrically arranged similarly as the ferroelectric memory cell described above relative to FIGS, la through lc, it has been observed that the polarization enhancement is increased by programming process 47 programming a "0" data state on the ferroelectric capacitor, as compared with process 47 programming a "1" data state. More specifically, in the arrangement of FIGS, la through Id in which a positive plate line voltage is applied to upper conductive plate 20b of FIG. la, the "0" data state (i.e., the state exhibiting the V(0) transition in FIG. Id) corresponds to the polarization state in the hysteresis diagram of FIG. lb.

Generally, this preferred polarization state programmed in process 47 is that for which the ferroelectric material is not polarized to the opposite state by the application of the read voltage.

[0050] While a preferred polarization state (e.g., the "0" data state) for programming process 47 may be exhibited by the ferroelectric structures, the less preferred polarization state (in this example, the "1" data state) may still exhibit some additional enhancement as compared with that resulting from cure process 48 for unpolarized (or "native") ferroelectric material. However, as noted above, significant enhancement in the polarization characteristics of the ferroelectric material is still attained even without the additional benefit of the pre-polarization of the ferroelectric material. Accordingly, programming process 47 is optional in this embodiment.

[0051] After cure process 48, assembly and test process 50 is then performed on the integrated circuits in a conventional manner. Assembly/test process 50 includes such assembly operations as the dicing of integrated circuits from wafer form, mounting of the individual dies to a lead frame or other package, wire bonding or other bonding to electrically connect the bond pads of the integrated circuit to leads of the eventual package, and completion of the package by molding (and curing) plastic mold compound around the lead frame and die or otherwise sealing the package, depending on the particular plastic or ceramic packaging technology being used. Electrical test of the packaged integrated circuit is then also performed as part of assembly/test process 50, including the exercise of the ferroelectric structures in those integrated circuits as appropriate for the desired device functionality. Assembly/test process 50 may also include the mounting of the packaged integrated circuit to a printed circuit board or other system implementation, such as by solder reflow or wave soldering, whether performed by the manufacturer of the integrated circuit or by a customer or other end user.

[0052] Some embodiments enable the packaging of ferroelectric integrated circuits in packages of the type referred to as wafer-chip-scale packages (WCSP). These packages are essentially at the size of the die itself, and rely on solder balls that are separated from the integrated circuit surface by polyimide or other passivation layers. The degradation of polarization characteristics resulting from conventional cure processes for these passivation layers has effectively precluded the use of WCSP technology for ferroelectric devices. However, the enhanced polarization performance, and the resulting improved read margin for FRAM devices in particular (as provided by the passivation cure processes implemented according to these embodiments), has enabled the use of WCSP technology for FRAMs and other ferroelectric devices.

[0053] FIG. 4 illustrates, in cross-section, a ferroelectric integrated circuit packaged in a WCSP package according to an embodiment. In this example, integrated circuit die 70 has its circuit components 72 formed at and near the semiconducting surface of its substrate, as described above in connection with the process flow of FIG. 2. As suggested generally in FIG. 4, these circuit components 72 include ferroelectric capacitors 55. Conductive pad 74 corresponds to a bond pad at the surface of die 70 and is electrically coupled with the active circuitry 72. First passivation layer 76 is a layer of a polyimide or other suitable passivation material that has been dispensed onto the surface of die 70 and patterned to expose a portion of pad 74 as shown. According to this embodiment, cure process 48 cures passivation layer 76 by heating the structure to a cure temperature below the Curie temperature of the ferroelectric material in capacitors 55, for a duration sufficient for passivation layer 76 to attain a tensile stress state, but not so long as to significantly degrade the polarization characteristics of the ferroelectric material, as described above.

[0054] Redistribution layer (RDL) 78 is a conductive layer deposited and patterned at the surface of first passivation layer to electrically couple with pad 74. As patterned, RDL layer 78 extends over the surface of first passivation layer 76 from pad 74 to a location at which external electrical contact is to be formed. In this example, second passivation layer 80, which is also of a polyimide or other suitable passivation material, is dispensed onto the surface of first passivation layer 76 and RDL layer 80, cured by cure process 48, and patterned to expose RDL 18 at a selected location. The stress exerted by second passivation layer 80 onto the ferroelectric material of capacitors 55 will be attenuated, considering that it is in indirect contact only with the surface of die 70 (i.e., via first passivation layer 76). Accordingly, the duration of the second instance of cure process 48 performed for second passivation layer 80 need only be of such a duration as to attain structural integrity. Alternatively, passivation layers 76, 80 may be dispensed and patterned before cure, such that a single instance of cure process 48 may be performed to place both layers into a tensile stress state that imparts compressive stress to the ferroelectric material of capacitors 55, without degrading the polarization characteristics of that material as described above.

[0055] The WCSP package of FIG. 3 is completed by the deposition and patterning of a conductive metal layer to form under bump metallization ("UBM") pad 82 at the location of the opening through second passivation layer 80 at which RDL 78 is exposed. Solder ball 84 is then formed at UBM pad 82, in a conventional manner. UBM layer 82 protects the exposed edges of second passivation layer 80 from delamination of second passivation layer 80 from the underlying RDL 78, which would provide a path for contamination and, in some situations, short circuits among elements of RDL 78. UBM 82 can also serve as a diffusion barrier to the material of solder ball 84.

[0056] Alternatively, if solder ball 84 can be formed over pad 74 at the surface of die 70, then only a single passivation layer 76 (and single instance of cure process 48) would be necessary.

[0057] In any event, the dispensing and curing of passivation layers (such as polyimide in the WCSP context, as described above relative to FIG. 4) according to these embodiments can enhance rather than degrade the polarization characteristics of ferroelectric material in circuit elements of the packaged integrated circuit die. Most (and perhaps all) ferroelectric dielectric materials also exhibit a piezoelectric effect, such that the ferroelectric characteristics of the material can be altered by applied stresses. Some combination of the stress applied by the cured passivation layer, the heat of the curing process, and the electric field within the ferroelectric capacitor permanently and physically reorients domains in the ferroelectric material in parallel with that electric field. This realignment of the domains enhances the polarization characteristics of the ferroelectric material, increasing the signal margin of the device. Also, because the curing of these passivation layers according to these embodiments is carried out in a way that does not significantly degrade the polarization characteristics of the ferroelectric material, the ferroelectric material is better able to tolerate the temperature exposure of solder ref ow in the mounting of the WCSP package to a printed circuit board. Indeed, it is believed that these embodiments enable ferroelectric integrated circuits to be packaged as WCSPs, which was not previously practicable due to the polarization degradation caused by the conventional polyimide cure and solder reflow processes.

[0058] Accordingly, by enhancing the polarization characteristics of ferroelectric materials, these embodiments can provide significant benefit to integrated circuits with ferroelectric materials. For example, the improved read margin provided by these embodiments enables the manufacture of FRAMs suitable for reliable use in a wider range of applications, such as in systems intended for elevated temperatures. Also, these embodiments improve the tolerance of the ferroelectric integrated circuits for high temperature processes (such as WCSP packaging, solder reflow and other mounting processes), without necessitating relaxation of the expected electrical performance and reliability specifications (e.g., circuit performance, device sizes) from what may otherwise be attainable for applicable technology nodes. If instead the ferroelectric integrated circuits are packaged in conventional molded plastic packages, the benefits of using polyimide as a stress relief agent are obtained, without suffering the degradation in polarization characteristics encountered from conventional cure processing. Also, these embodiments can enable the use of copper metallization and the resulting increased conductivity in the metal conductors relative to aluminum and other materials, despite the high hydrogen concentration in the silicon nitride barrier layer typically used with copper, because of the minimal thermal processing involved in curing the passivation layer as described above.

[0059] Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.