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Patent Searching and Data


Title:
LOW TEMPERATURE POLYCRYSTALLINE SILICON ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREFOR
Document Type and Number:
WIPO Patent Application WO/2019/000488
Kind Code:
A1
Abstract:
A low temperature polycrystalline silicon array substrate, comprising a low temperature polycrystalline silicon thin film transistor (10), a flat layer (20) above the low temperature polycrystalline silicon thin film transistor (10), a back side indium tin oxide layer (30), and an insulating layer (40) on a surface of the back side indium tin oxide layer (30). Scale marks are formed on the back side indium tin oxide layer (30) and are hollow patterns formed on the back side indium tin oxide layer (30); the insulating layer (40) is attached onto the surface of the back side indium tin oxide layer (30) and completely covers the scale marks, or the insulating layer (40) is hollowed out to expose a middle region of the scale marks. The manufacturing method for the low temperature polycrystalline silicon array substrate is easy, by specially designing the scale marks on the back side indium tin oxide layer (30) and the insulating layer (40) thereon, a shedding phenomenon of plasma silicon nitride can be effectively reduced, and the yield of substrate products is dramatically improved.

Inventors:
LIU FENGJU (CN)
Application Number:
PCT/CN2017/092507
Publication Date:
January 03, 2019
Filing Date:
July 11, 2017
Export Citation:
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Assignee:
WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO LTD (CN)
International Classes:
H01L27/12
Foreign References:
CN106169441A2016-11-30
CN106229347A2016-12-14
CN1787153A2006-06-14
CN102636962A2012-08-15
CN104078423A2014-10-01
CN105428332A2016-03-23
US6307611B12001-10-23
Attorney, Agent or Firm:
MING & YUE INTELLECTUAL PROPERTY LAW FIRM (CN)
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