Title:
LOW TEMPERATURE POLYSILICON THIN FILM TRANSISTOR ARRAY SUBSTRATE MANUFACTURING METHOD
Document Type and Number:
WIPO Patent Application WO/2016/145726
Kind Code:
A1
Abstract:
Provided is a low temperature polysilicon thin film transistor array substrate manufacturing method. The method comprises the following steps: (A) defining a heavily doped area (316a) and a lightly doped area (316b) of a source electrode of an n-channel, and a heavily doped area (317a) and a lightly doped area (317b) of a drain electrode of the n-channel using a photomask having a first pattern; (B) defining a doped area of a source electrode (318) and a doped area of a drain electrode (319) of a P-channel using a photomask having a second pattern; C) defining a pixel area, a contact hole area of the heavily doped area of the drain electrode (317a) and the heavily doped area of the source electrode (316a) of the n-channel, and a contact hole area of the doped area of the source electrode(318) and the doped area of the drain electrode(319) of the P-channel using a photomask having a third pattern; and D) defining a metal electrode area of the heavily doped area of the drain electrode (317a) and the heavily doped area of the source electrode(316a) of the n-channel, and a metal electrode area of the doped area of the source electrode (318) and the doped area of the drain electrode(319) of the P-channel using a photomask having a fourth pattern.
Inventors:
LU MACAI (CN)
Application Number:
PCT/CN2015/077964
Publication Date:
September 22, 2016
Filing Date:
April 30, 2015
Export Citation:
Assignee:
SHENZHEN CHINA STAR OPTOELECT (CN)
International Classes:
H01L27/12; H01L21/77
Domestic Patent References:
| WO2011161910A1 | 2011-12-29 |
Foreign References:
| CN101752319A | 2010-06-23 | |||
| CN1632857A | 2005-06-29 | |||
| CN104157608A | 2014-11-19 |
Attorney, Agent or Firm:
MING & YUE INTELLECTUAL PROPERTY LAW FIRM (CN)
深圳市铭粤知识产权代理有限公司 (CN)
深圳市铭粤知识产权代理有限公司 (CN)
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