Title:
LOW THERMAL RESISTANCE AND ROBUST CHIP-SCALE-PACKAGE (CSP), STRUCTURE AND METHOD
Document Type and Number:
WIPO Patent Application WO/2010/129091
Kind Code:
A3
Abstract:
A chip scale package (CSP) semiconductor device can include a semiconductor layer, circuitry on an active surface of the semiconductor layer, and a diamond layer on a back side of the semiconductor layer. The diamond layer can provide an efficient heat sink for the semiconductor layer, with a thermal conductivity which can be more than three times greater than the thermal conductivity of copper. Further, a hardness of the diamond layer {up to about 10 times stronger than silicon) can provide effective protection against damage to the exposed semiconductor layer, for example during manufacturing, handling, and use of the CSP device. Thus a thin protective diamond layer can be used, which can result in a very thin CSP package design.
Inventors:
HEBERT FRANCOIS (US)
KELKAR NIKHIL (US)
KELKAR NIKHIL (US)
Application Number:
PCT/US2010/026820
Publication Date:
January 13, 2011
Filing Date:
March 10, 2010
Export Citation:
Assignee:
INTERSIL INC (US)
HEBERT FRANCOIS (US)
KELKAR NIKHIL (US)
HEBERT FRANCOIS (US)
KELKAR NIKHIL (US)
International Classes:
H01L23/48; H01L23/36
Foreign References:
| US20050179126A1 | 2005-08-18 | |||
| US20040157386A1 | 2004-08-12 | |||
| US20030183823A1 | 2003-10-02 | |||
| US20040238946A1 | 2004-12-02 |
Attorney, Agent or Firm:
FOGG, David, N et al. (5810 W. 78th St. Ste 100Minneapolis, MN, US)
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