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Title:
LOW-VOLTAGE DIFFERENTIAL SIGNALING OR 2-WIRE DIFFERENTIAL LINK WITH SYMBOL TRANSITION CLOCKING
Document Type and Number:
WIPO Patent Application WO/2015/103009
Kind Code:
A1
Abstract:
Systems, methods and apparatus are described for use in a communications link having a number of connectors. A method for communication using differential signaling with symbol transition clocking signaling communicates symbols over a communications link without transmitting a clock signal in a dedicated lane of the communications link. At a receiver, clock information may be extracted without using a phase-locked loop. The method includes converting data bits into a plurality of transition numbers, converting the plurality of transition numbers into a sequence of symbols, and transmitting the sequence of symbols over a plurality of signal wires. A clock signal may be embedded in transitions between consecutive symbols in the sequence of symbols. Each consecutive pair of transition numbers in the plurality of transition numbers may include two transition numbers that are different from one another. The sequence of symbols may be transmitted as a plurality of differential signals.

Inventors:
SENGOKU, Shoichiro (5775 Morehouse Drive, San Diego, California, 92121-1714, US)
Application Number:
US2014/071958
Publication Date:
July 09, 2015
Filing Date:
December 22, 2014
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
QUALCOMM INCORPORATED (ATTN: International IP Administration, 5775 Morehouse DriveSan Diego, California, 92121-1714, US)
International Classes:
H04L25/49; H04L7/033; H04L25/493
Domestic Patent References:
WO2008151251A12008-12-11
WO2008109478A22008-09-12
Foreign References:
US20090092212A12009-04-09
US20050141661A12005-06-30
Other References:
None
Attorney, Agent or Firm:
LOZA, Julio (Loza & Loza LLP, 305 North Second Avenue #127Upland, California, 91786, US)
Download PDF:
Claims:
1. A method for multi-wire signaling, comprising;

receiving data to be communicated over a communications link using differential signaling;

converting the data to a set of transition numbers;

selecting sequences of symbols using the transition numbers; and

transmitting the sequence of symbols over a plurality of lanes in the

communi cations 1 ink,

wherein each symbol corresponds to a signaling state of a plurality of lanes on the communications link, and

wherein each pair of consecutive symbols hi the sequences of symbols comprises two differeiii symbols such that transmitting the two different symbols causes a transition in signaling state of at least one lane in the communications link.

2. The method of claim 1, wherein clock information is embedded in transitions in signaling state of the plurality of lanes occurring between symbols consecutively transmitted on the communications link.

3. The method of claim 1 , wherein the seque ce of symbols is transmitted as a plurality of signals, each signal being transmitted over one of the plurality of lanes.

4. The method of claim 1, wherein each lane comprises a pair of differe tial signal wires, and wherein transmitting the sequence of symbols comprises:

providing a differential signal to each lane, the differential signal corresponding to a bit position in each symbol of the sequence of symbols.

5. The method of claim 1 , wherein the sequence of symbols is transmitted without transmitting a clock signal in a dedicated clock lane on the communications link.

6. The method of claim I , wherein transmitting the sequence of symbols comprises: repurposmg a clock lane of the communications link to cany a differential signal corresponding to one bit of symbols transmitted on the communications link.

7. The method of claim I , wherein transmitting the sequence of symbols comprises:

using low voltage differential drivers to transmit the sequence of symbols.

8. An apparatus for multi-wire signaling, comprising:

a plurality of differential transmitters adapted to couple the apparatus to a commun cations link that employs differential signaling;

a first converter that is configured to receive data to be communicated over the communications link and to convert the data to a set of transition numbers; and

a second converter that is configured to select sequences of symbols using the transition numbers,

wherein each sequence of symbols is transmitted on the communications link using the plurality of differential transmitters,

wherein each pair of consecutive symbols in the sequences of symbols comprises two different symbols that define different signaling states of the

communications link.

9. The apparatus of claim 8, wherein the second convenor is configured to embed clock information in transitions in signaling state of the communications link by selecting consecutively transmitted, pairs of symbols that are different from one another.

10. The apparatus of claim 8, wherein the plurality of differential transmitters comprises n transmitters configured to produce 2 signaling states such that 2" symbols are available for transmission on the communications link, and wherein the first convertor is configured encode data using r = 2n- 1 transition numbers.

11. The apparatus of claim 10, wherein each sequence of symbols comprises m symbols, and wherein each sequence of symbols encodes data elements that have up to (2H-ir possible states.

12. The apparatus of claim 8, wherein the plurality of differential transmitters comprises low voltage differential transmitters.

13. The apparatus of claim 8, wherein each symbol comprises a plurality of bits, each bit controlling a signaling state output by one of the plurality of differential transmitters.

14. The apparatus of claim 8, wherein each sequence of symbols is transmitted based on timing provided by a transmit clock, and wherein the transmit clock is not transmitted in a dedicated clock lane on the communications link

15. The apparatus of claim 8, wherein each sequence of symbols is transmitted on the communications link using low voltage differential signaling.

16. The apparatus of claim 8, wherein in a different mode of operation, one of the plurality' of differential transmitters carries a clock signal and other transmitters in the plurality of differential transmitters carry signals representative of different bits of the data.

17. A receiving apparatus for multi-wire signaling, comprising:

a plurality of differential receivers configured to provide a sequence of symbols representative of signals received from a plurality of lanes in a communications link; a clock recovery circuit adapted to generate a receive clock by detecting transitions in signaling state of the communications lixik, wherein the transitions in signaling state of the communications link correspond to transitions between symbols in the sequence of symbols;

a first converter configured to generate a set of transition numbers representative of difference between consecutive symbols in the sequence of symbols; and

a second converter configured to decode data from the set of transition numbers.

18. The receiving apparatus of claim 17, wherein edges of the receive clock correspond, to transitions between symbols in the sequence of symbols.

19. The receiving apparatus of claim 17, wherein the receive clock is used to capture the sequence of symbols.

20. The receiving apparatus of claim 17, wherein the clock recovery circuit generates the receive clock without using a phase -locked loop.

21. The receiving apparatus of claim 17, wherein one or more operations of the first converter and. o e or more operations of the second converter are controlled by the receive clock.

22. The receiving apparatus of claim 17, wherein plurality of differential receivers comprises low voltage differential receivers.

23. The receiving apparatus of claim 17, wherein the communications link is configured for low voltage differential signaling.

24. A method, for multi-wire signaling, comprising:

receiving a sequence of symbols from a plurality of lanes in a differential signaling communications link;

extracting a receive clock corresponding to transitions between consecutive symbols in the sequence of symbols;

generating a set of transition numbers, each transition number represe tative of difference in signaling states of the communications link corresponding to each pair of consecutive sequences of symbols in the sequence of symbols; and

converting the set of transition numbers to data,

wherein each pair of consecutive symbols in the sequences of symbols comprises two different symbols such the clock includes an edge corresponding to each symbol in the sequence of symbols.

25. The method of claim 24, wherein edges of the receive clock correspond to transitions between symbols in the sequence of symbols.

26. The method of claim 24, further comprising;

capturing the sequence of symbols using the receive clock.

27. The method of claim 24, the receive clock is extracted without using a phase- locked loop.

28. The method of claim 24, further comprising;

using the receive clock to control generation of the set of transition numbers; and using the receive clock to control conversion of transition numbers to data.

29. The method of claim 24, wherein the sequence of symbols is encoded in a plurality of differential signals, each differential signal being received from a different lane of the communications link.

30. The method of claim 24, wherein the differential signaling communications link employs low voltage differential signaling.

Description:
LOW-VOLTAGE DIFFERENTIAL SIGNALING OR 2-WIRE DIFFERENTIAL

LINK WITH SYMBOL TRANSITION CLOCKI G

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to and the benefit of patent application no. 14/577,897, which was filed in the United States Patent Office on December 19, 2014, which claims priority to and the benefit of provisional patent, application no, 61/923,456, which was filed in the United States Patent Office on January 3, 2014, the entire content of which is incorporated herein by reference.

Field

[0002] The present disclosure pertains to transmitting and/or encoding a clock signal within cycles of a multi-signal data transfer.

Background

[0003] The Mobile Industry Processor Interface (MIPI*) Alliance has been defining standards for serial interfaces, including physical layer (PHY) standards that may be used in mobile devices to provide high bandwidth connections between devices and peripherals within mobile devices. The MIPI standards include the D-PHY standard (referred to herein as MIPI D-PHY, or DPHY) that employs a signaling scheme which requires a dedicated clock lane to provide a receiving device with timing information used by a transmitting device to transmit data. The MIPI standards include the M-PHY standard, (referred to herein as MIPI M-PHY, or MPHY) that employs a signaling scheme ixi which the transmitter embeds the timing information in the transmitted data and. the receiver extracts the timing information using a phase-locked loop (PLL) to provide a receive clock.

[0004] The use of a dedicated clock lane requires using at. least one extra conductor and the use of PLLs to extract, clocks embedded in the data lanes increases the complexity of the receiver circuitry, particularly when the PLLs must rapidly synchronize on received data signals. SUMMARY

Systems, methods and apparatus are disclosed herein thai use a communications link having a number of connectors. The communications link may be provided between two devices, which may be collocated in an electronic apparatus. Certain aspects of the invention provide an efficient method for embedding clock signals within multi-wire communication interfaces, including communication interfaces that employ differential signaling. In one example, a differential signaling system may be provided that does not require a dedicated clock lane. In another example, receivers may be constructed without a PLL for recovering a clock used to decode data transmitted on the communi cation interface.

According to certain aspects, a method for multi-wire signaling includes receiving data to be communicated over a communications link using differential signaling, converting the data to a set of transition numbers, selecting sequences of symbols using the transition numbers and transmitting the sequence of symbols over a plurality of lanes in the communications link. Each symbol may correspond to a signaling state of a plurality of lanes on the communications link. Each pair of consecutive symbols in the sequences of symbols may include two different symbols. Transmitting the two different symbols causes a transition in signaling state of at least one lane in the communications link. In an aspect, clock information is embedded in transitions in signaling state of the plurality of lanes occurring between symbols consecutively transmitted on the communications link. The sequence of symbols may be transmitted as a plurality of signals, each signal being transmitted over one of the plurality of lanes.

In an aspect, each lane include a pair of differential signal wires. The sequence of symbols may be transmitted by providing a differential signal to each lane. The differential signal may correspond to a bit position in each symbol of the sequence of symbols.

In an aspect, the sequence of symbols may be transmitted without transmitting a clock signal in a dedicated or separate lane in the communications link. A signaling lane used as a clock lane in some modes of operation of the communications link may be repurposed to cany a differential signal corresponding to one bit of symbols transmitted on the communications link.

According to certain aspects, an apparatus for multi-wire signaling includes a plurality of differential transmitters adapted to couple the apparatus to a communications link that employs differential signaling, a first converter that is configured to receive data to be communicated over the communications link and to convert the data to a set of transition numbers, and a second convenor that is configured to select sequences of symbols using the transition numbers. Each sequeiice of symbols may be provided to the plurality of differential transmitters. Each pair of consecutive symbols in the sequences of symbols may include two different symbols that define different signaling states of the communications link. The differential transmitters may include low voltage di fferen tial transm it ters.

[0011] In an aspect, the second converter is configured to embed clock information in transitions in signaling state of the communications link by selecting consecutively transmitted pairs of symbols that are different from one another.

[0012] In an aspect, the plurality of differential transmitters may include n transmitters configured to produce 2 signaling states such that 2" symbols are available for transmission on the communications link data. The first converter may be configured encode data using r = 2"-l transition numbers. Each sequeiice of symbols may include m symbols. Each sequence of symbols may encode data elements that have up to (2"-\) m possible states.

[0013] In an aspect, each symbol includes a plurality of bits. Each bit may control a signaling state output by one of the plurality of differential transmitters,

[0014] In an aspect, the apparatus provides no clock signal in a dedicated clock lane on the communications link. In a different mode of operation, one transmitter of the plurality of differential transmitters carries a clock signal and other transmitters in the plurality of differential transmitters cany signals representative of different bits of the data.

[0015] According to certain aspects, a receiving apparatus for multi-wire signaling, includes a plurality of differential receivers configured to provide a sequence of symbols representative of signals received from a plurality of lanes in a differential signaling communications link, a clock recovery circuit adapted to generate a receive clock by detecting transitions in signaling state of the communications link, a first converter configured to generate a set of transition numbers representative of difference between consecutive symbols in the sequence of symbols, and a second, converter configured to decode data from the set of transition numbers. The transitions in the signaling state of the communications link coirespond to transitions between symbols in the sequence of symbols.

[0016] In an aspect, edges of the receive clock correspond to transitions between symbols in the sequence of symbols. The receive clock may be used to capture the sequence of symbols. One or more operations of the first convertor and/ or one or more operations of the second convertor are controlled by the receive clock.

[0017] According to certain aspects, a method for multi-wire signaling includes receiving a sequence of symbols from a plurali y of lanes in a differential signaling communications link, extracting a clock corresponding to transitions between consecutive symbols in the sequence of symbols, generating a set of transition numbers, each transition number representative of difference in signaling states of the communications link corresponding to each pair of consecutive sequences of symbols in the sequence of symbols, and converting the set of transition numbers to data. Each pair of consecutive symbols in the sequences of symbols includes two different symbols such the clock includes an edge corresponding to each symbol in the sequence of symbols.

[0018] In an aspect, edges of the receive clock correspond to transitions between symbols in the sequence of symbols.

[0019] In an aspect, the method includes capturing the sequence of symbols using the receive clock. The first convertor may be controlled using the receive clock. The second convertor may be controlled using the receive clock.

[0020] In an aspect, the sequence of symbols may be encoded in a plurality of differential signals, each differential signal being received from a different lane of the communications link.

DRAWINGS

[0021] Various features, nature and advantages may become apparent from the detailed. description set forth below when taken in conjunction with the drawings in which like reference characters identify correspondingly throughout.

[0022] FIG. I illustrates a single-ended signaling system,

[0023] FIG. 2 is a block diagram illustrating an example of a transmitter device.

[0024] FIG. 3 is a block diagram illustrating an example of a receiver device.

[0025] FIG. 4 illustrates a timing diagram corresponding to the transmitter and receiver devices of FIGS. 2 and 3.

[0026] FIG. 5 is a block diagram illustrating one example of a clock and data recovery circuit

(CDR) and a corresponding timing diagram.

[0027] FIG. 6 illustrates examples of cell delays P and S that may be used with the CD circuit of FIG. 5.

[0028] FIG. 7 illustrates examples of registers that may be used with the CDR circuit of FIG. 5. [0029] FIG. 8 illustrates examples of communications links that employ differential signaling.

[0030] FIG. 9 is block diagram and timing chart illustrating the operation of a CDR circuit in a communications link configured according to certain aspects disclosed herein.

[0031] FIG. 10 illustrates the conversion from bits to transition numbers at a transmitter and then from transition numbers to bits at a receiver.

[0032] FIG. 1 1 illustrates one example of conversion between sequential symbols and transit! oxi numbers.

[0033] FIG. 12 illustrates a utilization table for a 2-lane, 4-wire differential system that uses ail of the 3 available states per symbol for various symbols per group.

[0034] FIG. 13 illustrates a utilization table for a 3-lane, 6-wire differential system that uses all of the 7 a vailable states per symbol for various symbols per group.

[0035| FIG. 14 illustrates a utilization table for a 3-iane, 6-wire differential system that uses 6 available states per symbol (after reserving 1 state for a special purpose) for various symbols per group.

[0036] FIG. 15 illustrates a utilization table for a 4-lane, 8-wire differential system that uses ail of the 15 available states per symbol for various symbols per group.

[0037] FIG. 16 illustrates a utilization table for a 4-lane, 8-wire differential system that uses 14 available states per symbol (after reserving 1 state for a special purpose) for various symbols per group.

[0038] FIG. 17 illustrates a utilization table for a 5-iane, 10-wire differential system that uses all of the 31 available states per symbol for various symbols per group.

[0039] FIG. 18 illustrates a utilization table for a 5-lane, 0-wire differential system that uses 30 available states per symbol (after reserving 1 state for a special purpose) for various symbols per group.

[0040] FIG. 19 illustrates a utilization table for an 8-lane, 16-wire differential system that uses all of the 255 available states per symbol for various symbols per group.

[0041] FIG. 20 illustrates a utilization table for an 8-lane, 16-wire differential system that uses

254 available states per symbol (after reserving 1 state for a special purpose) for at various symbols per group.

[0042] FIG. 21 is a block diagram illustrating an example of an apparatus employing a processing circuit that may be adapted according to certain aspects disclosed herein.

[0043] FIG. 22 is a flow chart of a method of encoding for low-voltage differential signaling.

[0044| FIG. 23 is a diagram illustrating an example of a hardware implementation for an encoding apparatus employing low-voltage differential signaling. FIG. 24 is a flow chart of a method of decoding for low-voltage differential signaling, FIG. 25 is a diagram illustrating an example of a hardware implementation for a decoding apparatus for use with low-voltage differential signaling.

DETAILED DESCRIPTION

In the following description, specific details are given to provide a thorough understanding of the embodiments. However, it will be understood by one of ordinary skill in the art that the embodiments may be practiced without these specific detail. For example, circuits may be shown in block diagrams in order not to obscure the embodiments in unnecessary detail. In other instances, well-known circuits, structures and techniques may not be shown in detail in order not to obscure the embodiments. Systems, devices and methods for embedding a clock signal within a communication interface are provided. According to certain aspects disclosed herein, the communication interface may include a plurality of wires or other connectors. In one example, the plurality of wires may be configured to provide a differential signaling system. In another example, the plurality of wires is configured to provide a single- ended signaling system. In order to simplify descriptions of certain aspects of the invention, some examples are provided, that relate to a single-ended signaling system, and other examples are provided that relate to differential signaling systems. It will be appreciated that the selection of examples does not limit the scope of the invention and the principles illustrated with respect to one signaling system may relate equally to other signaling systems,

Multi-Wire Single-Ended Push-Puil Link with Data Transition Based Clocking FIG. 1 illustrates a single-ended signaling system. In single-ended signaling, one wire carries a varying voltage that represents the signal, while another wire may be connected to a reference voltage (e.g., ground). A transmitter device 102 may include one or more single-ended push-pull complementary metal-oxide-semiconductor (CMOS) drivers 108, with each driver 108 being coupled to a single wire/conductor 106a, 1 06b, 106c, and/or 106d. A receiver device 104 may include one or more single-ended receivers 110, with each single-ended receiver 1 10 being coupled to a single wire/conductor 106a, 106b, 106c, and/or 106(1 The transmitter device 102 receives input bits 118, encodes them (at encoder 122) into single-ended signals, and transmits them to the receiver 104 as single- ended signals through the single-ended drivers 108 via each wire/conductor 106a, 106b, 106c, and/or 106d. The receiver device 104 receives the single-ended signals via each wire/conductor 106a, 106b, 106c, and/or 106d through the single-ended receivers 1 10, decodes the single-ended signals (at decoder 124), and provides output bits 120. In this single-ended system, the decoder 124 may include a dock and data recover}' (CDR) such that a clock signal is extracted from one or more received single- ended signals.

[0050] FIG. 2 is a block diagram illustrating an example of a transmitter device. The encoder 122 may include a bits-to-/wxT converter 202 that converts binary formatted data (bits) 118 into m multiple transition numbers, TO, Tl , Tm-1. A T-to-S converter 204 then converts the transition number T 203 into a symbol number current state Cs 205. A first flip-flop 206 stores the current state Cs 205 at each symbol clock TXCLK 210, and provides a previous symbol Ps 207 to the T-to-S converter 204. A second flip-flop 208 samples in the current state Cs and generates output state data to the n CMOS type drivers 108.

[0051] FIG. 3 is a block diagram 300 illustrating an exemplary receiver device. A plurality of n CMOS type single-ended receivers 110 serve to receive data on n-wtre channels as symbol input current state Cs 305. A clock and data recovery circuit (CDR) 302 serves to recover a symbol clock RXCLK 310 from the symbol input from the receivers 1 10, and registers the valid data to be used, by the rest of the decoder 124. A plurality of n flip-flops 308 stores the current state Cs 305 at each rising edge of the clock RXCLK 310 and generates a previous state Ps 307. An S-to-T converter 304 generates a sequential transition number T 303 by comparing the current state Cs 305 and the previous state Ps 307. A mxT-to-Bits converter 306 converts m multiple transition numbers, TO, Tl, Tm- 1, into a binary format data to be output as bits 120.

[0052] FIG. 4 illustrates a timing diagram of the transmitter and receiver devices of FIGS. 2 and 3.

[0053| At the transmitter device 102, original input data 1 18 in bits format, Dn (DO, Dl, D2, ...), is converted to multiple numbers of transition numbers, TnO, Tnl , Tn4 as a signal T 203 by the Bits-to-mxT converter 202 at every rising edge of the transmitter clock signal TXCLK 210, The signal T 203 is converted into the current state Cs (e.g., SnO, Snl, Sn2, Sn4) by the T-to-S converter 204. The current state Cs signal is sampled at every rising edge of the transmitter clock signal TXCLK 210, and the n CMOS (push-pull) drivers 108 output the sampled data to the «-wire communication link (e.g., n conductors). [0054] At the receiver device 104, the signal on the w-wire communication link (e.g., n conductors) is received by the n receivers 1 10 whose output is fed to the clock and data recovery circuit CDR 302 to recover the link clock RXCLK 310, and output valid data at every rising edge of the RXCLK 310 to be fed to the S-to-T converter 304 to convert the each of the symbol states (e.g., SnO, Snl, Sn2, Sn4) 305 into transition numbers T 303 (e.g., TnO, Tnl , Tn4). The transition numbers T 303 (e.g., TnO, Tnl, Tn4) is fed to the wxT-to-B s converter 306 to restore the bits information 120.

[0055] FIG. 5 includes a block diagram 500 illustrating one example of a clock and data recovery circuit CDR 501 and a corresponding timing diagram 540. This CDR circuit 501 includes a comparator 504, a set-reset register 506, a first delay device/element 502, a one-shot logic 502/503, a second delay device/element 508, and a register 510. The first delay device/element 502 and/or second delay device/element 508 may be either a digital delay or an analog delay. The comparator 504 may compare a first instance of the first state transition signal (SI) and a registered instance of the first state transition signal (S) and outputs a comparison signal (NE signal) 514. The set-reset register 506 may receive the NE signal 514 from the comparator 504 and outputs a filtered version of the comparison signal (NEFLT signal) 18. The first delay device/element 502 may receive the NEFLT signal 518 and output a delayed instance of the filtered version of the comparison signal (NEDEL signal) 526. The one-shot logic 502/503 may receive NEFLT signal 518 and the NEDEL signal 526 and output a second filtered version of the comparison signal ( E1.SHOT signal) 524. The second delay device/element 508 may receive the NE1SHOT signal 524 and output, a delayed instance of the RXCLK SIGNAL 516. The set-reset register 506 may be reset based on the delayed instance of the RXCLK SIGNAL 516. The register 510 may receive the first state transition signal (SI) and outputs the registered instance of the first state transition signal (S), where the register 510 is triggered based on the delayed instance of the RXCLK SIGNAL 516.

[0056] As can be appreciated from the timing diagram 540, the small delay P 502 introduced provides more margins for setup time between symbols.

[0057] The following definitions are used in the timing diagram 540 signal:

t syni : one symbol cycle period,

t S Tj: setup time of SI for the register 10 referenced to the rising (leading) edge of

RXCLK SIGNAL 516,

½ hold time of SI for the register 510 referenced to the falling (trailing) edge of RXCLK SIGNAL 516, i E ' propagation delay of the comparator 504,

tdRs-r: reset time of the set-reset register 506 from the rising (leading) edge of

RXCLK SIGNAL 516,

t d is: propagation delay of the one-shot logic 503.

[0058| Initially, signals SI and S hold the previous symbol value SymO 522. The NE signal

514, NEFLT signal 518, and SDRCLK are zero.

[0059] When a new symbol value Syml 544 is being received, it causes signal SI to start changing its value. The SI value may be different from Syml 544 (valid data) due to the possibility of receiving intermediate or indeterminate states 546 of the signal transition (from SymO to Syml ) that may be caused, for example, by inter- wire skew, over/under shoot, cross-talk, etc.

[0060J The NE signal 514 becomes high as soon as the comparator 504 detects different value between SI and S, and that (synchronously/asynchronously) sets the set-reset register 506 output, NEFLT signal 518, high after tdNE, which hold its high state until it is reset by a high state of RXCLK SIGN AL 516 which will arrive approximately a Delay period S (caused by delay S 508) after rising of NEFLT signal 518.

[0061] The intermediate states 546 at SI (invalid data) may contain a short period of symbol value SymO 522 causing the NE signal 514 to return low for short periods of time (spikes 558 in the NE signal 514). The low state of the NE signal 514 will not affect the set-reset register 506 output, NEFLT signal 518, since the set-reset register 506 effectively filters out spikes on the NE signal 514 before outputting the NEFLT signal 518.

[0062] The one-shot circuit (logic gate 503 with delay P 502) generates a high state on its output, NEI SHOT signal 524, after tdi S from rising edge of NEFLT signal 51 8, and holds the NEI SHOT signal 524 at a high state for the Delay P period 502 before turns it to a low state.

[0063] The high state of NEISHOT signal 524 propagates to the RXCLK signal 516 after a

Delay S period 562 caused by the delay S 508.

[0064] The high state of RXCLK signal 516 resets the set-reset register 506 output, NEFLT signal 518, to low after rdRST. The high state of RXCLK signal 516 also enables the register 510 for the SI signal 520 value to be output as the S signal 522.

[0065] The comparator 504 detects when the S signal (symbol Syml 552) and matches the symbol Syml 544 of the SI signal 520, and turns its output, the NE signal 514, to low. [0066] The low state of E1SHOT signal 524 propagates to the RXCLK signal 516 after a Delay period S 562 caused by the delay S 508.

[0067] When a new symbol value Sym2 is being received, it causes the SI signal 520 to start changing its value to the next symbol Sym2 540 after tHD from the last falling (trailing) edge 564 of a pulse on the RXCLK signal 516.

[0068] The timing constraint for the symbol cycle period tsYM ma be as follows:

dNE + dis + Delay S + Delay P + t HD < ί 8ΥΜ .

More specifically, the symbol cycle time†SYM must be greater than total of: a Dela - period S, a Delay Period P, ½> > ¾ E, IS and t<iRST- If the total of these six time periods exceeds the ISYM period, the trailing edge of RXCLK SIGNAL 516 overlaps the next symbol cycle, disabling the NEFLT signal 518 from being set for the overlapping period. Note that the amount of overlapping period accumulates cycle by cycle and eventually results in an extra pulse on the RXCLK signal 16 in one symbol cycle.

[0069] The timing constraint for the setup time tsu may be as follows:

Max. skew spec + tsu < Delay S.

[0070] More specifically, the delay period S must be less than the setup time tsu pins the maximum skew.

[0071] FIG. 6 illustrates example 600, 620s of cell delays P and S that may be used with the CDR circuit 500 of FIG. 5. In the first example 600, a link whose data rate is slow enough, an internal system clock 612 can be used to implement digital delay cells. Delay P and Delay S. In the example, a source signal 602 may be clocked through a series of registers 604 and. a multiplexer 608 may be controlled by a delay select signal 606 to select an output of one of the series of registers 604 as the output delayed signal 610. In the example 620, a link whose data rate is fast, analog delays may be provided by buffers 624 or the like may be used to implement delay cells, Delay P a d Delay S. In the example, a source signal 622 may be clocked through the buffers 624. and a multiplexer 628 may be controlled by a delay select signal 626 to select an output of one of the buffers 624 as the output delayed signal 630.

[0072] FIG. 7 illustrates examples 700, 720 of registers 510 and 506 that may be used with the CDR circuit 500 of FIG. 5. In the first example 700, a link whose data rate is slow enough may use an internal system clock 706 to implement a register 510 that samples raw symbol input signals 520 and outputs the S signal 522. In the second example 720, the R-S register 506 may use an internal system clock 726 to generate glitch free (filtered) version of ME signals that are fully synchronous with the system clock 726. The R-S register 506 is implemented with, priority for the R input 724 over the S input 722. For the link whose data rate is fast, asynchronous level latches may be used to sample raw symbol input signals and an asynchronous R-S latch for the filtered NE signal 514 generation may be used.

Low-Voltage Differential Signaling Communications Links

Certain aspects described herein with respect to single-ended communications links may be adapted for use in communications links that are configured for differential signalmg schemes. FIG. 8 includes a block drawing 800 illustrating a conventional low-voltage differential signaling (LVDS) communications link. Typically, the LVDS communications link has one or more pairs of wires (differential pairs) 802, 804, each pair of wires carrying a pair of complementary signals. For example, data may be encoded in a first pair of wires 802 and a transmission clock may be transmitted in a second pair of wires 804. LVDS can reduce or eliminate common-mode noise when the wires in each pair of wires 802 or 804 are in close proximity to the other wire in the pair of wires 802 or 804. In one example, a pair of wires 802, 804 may include a twisted pair of wires that interconnect two or more devices. In another example, a pair of wires 802, 804 may be provided in close proximity within a semiconductor integrated circuit (IC) device, on a substrate carrying one or more IC devices, and/or on a printed circuit board or the like. LVDS can improve resistance to electromagnetic interference, particularly common-mode interference that has significant power and/or amplitude in comparison to the power and/or amplitude of the signals transmitted on the signal wires of a communications link.

In some instances, clocking information may be embedded in transmitted data. FIG. 8 includes a block diagram 820 illustrating a transmitter 822 and receiver 832 configured to support an encoding scheme that transmits data on a differential communications link 830 that does not have a separate and/or dedicated clock lane. In the transmitter 822, encoders 826 encode 8-bit transmission data 824 in a line code such as the 8b 10b code that may be used to map 8-bit symbols to 10-bit symbols. The 8b 10b code may provide direct current balance (DC-balance) with sufficient signaling state transitions to permit clock recovery at the receiver 832. The outputs of the encoders 826 may be provided through output control logic 828 to differential line drivers 840 coupled to a differential communications link 830. In one example, the differential communications link 830 is an LVDS link. [0075] The use of the 8b 10b code may ensure sufficient signaling state transitions on each of the differential signals transmitted over the differential communications link 830 such that PLL and deserialization (DES) circuits 838 in the receiver 832 can synchronize a receive clock to the clock used by the transmitter 822 for transmitting on the differential communications link 830 based on transitions in the signals received by the differential receivers 842. The 8bl 0b code provides run-length control such that same bit state is not permitted to continue too long in order to maintain the PLLs 838 in lock. Tn some instances, the 8b 10b code may enforce a limit of up to five consecutive bits to be the same. The 10b8b decoders 836 may be adapted to produce received data 834 correspondixig to the transmission data 824.

[0076] The PLL, and DES circuits 838 must typically be capable of achieving a fast synchronization lock to ensure reliable decoding of data received from the communications link 830. A receiver 832 may be required to have multiple internal predefined reference clocks that permit a PLL to be designed with a short period lock. The predefined reference clocks may have different frequencies or phase with respect to one another. The predefined reference clocks may limit the number of possible valid, clock rates for the communications link 830. Thus, the use of predefined reference clocks can increase PLL circuit, complexity and can limit the flexibility of operation of the communications link 830.

LVDS Communications Links Adapted For Symbol Transition Based Clocking [0077] FIG. 9 includes a diagram 900 illustrating a combination of an encoder 902 and. a decoder 912 that can support a variety' of signaling schemes, including LVDS, without the use of a PLL associated with each transmitted signal. The transmitter 902 may include a converter 906 that converts a number of bits of binary formatted transmission data 904 into m multiple transition numbers (TO, Tl, Tm-1). A transition number to symbol converter 908 then converts transition numbers into /? -bit symbols. In one example, the n-bit symbols may be transmitted by the LVDS drivers 924 or other differential drivers on n pairs of wires in the communications link 910.

[0078] The decoder 912 may be configurable to handle various signaling schemes, including single-ended, differential and other signaling schemes. In the example depicted, differential receivers 926 receive n pairs of differential signals from the n pairs of wires in the communications link 91 0. The differential receivers 926 provide an n-bit signal to a CDR 914, which extracts clock information and determines the symbol value from the n signals in each transmission cycle. A sequence of symbol values is provided to a converter 916 thai converts the sequence of symbol values into m multiple transition numbers (TO, T I , Trn-1 ). The m multiple transition numbers are provided to a decoder 918 that converts the m multiple transition numbers to bits of binary formatted data 920 representative of the transmission data 904.

Conversion Between Bits and Transition Numbers

[0079] FIG. 1 0 illustrates an example of conversion from transmission data bits to transition numbers at a transmitter 1000 and from transition numbers to received data bits at a receiver 1020. A transition number may include one or more digits, where each digit is used to select a next symbol to be transmitted based on a symbol that is being currently transmitted. Symbols may be transmitted as differentia] signals over a desired or selected pairs of differential wires. The example of FIG, 10 illustrates transmission on a communication interface that has lanes, such as an interface that uses a 4-wire differential signaling system, or an interface that uses a 2 -wire single-ended signaling system. The transmitter 1000 feeds binary information, Bits, into a "Bits-to-mxT" converter 1006 to generate m symbol transition numbers, To to T m ..j . The receiver 1020 receives the m symbol transition numbers, To to T m- i , which are fed into an "mxT-to- Bits" converter 1024 in order to retrieve the binary information (i.e., the Bits) encoded therein. For example, when there are r possible symbol transition states per time interval T, designated as T¾ Tj , . . . T m- ] , m transitions can provide r " different states. For an n differential pair (2n wire differential) communications link, r— 2"-l . Consequently, transitions T ¾ T ' i, . . . Τ,,,.ι contain data that can have (2"-l )' * " different states.

[0080] i one example, it may be assumed the possible symbol transitions for each time interval T, r =10. Assuming that the number of symbols in a group m = 3, such that the transition symbol is T 2 , Ti, To, where T<: 0, 1 , 2, 9. Each T can have 10 different states and the transition symbol for T 2 , ΊΊ, To may be for example, a 3-digit number, such as T;r=3, 1 · ' ) . To=l (or the decimal number 391). In this manner a sequence of bits may be converted into a plurality of transition numbers and vice versa.

[0081] In an example, where the number of lanes «=2 (e.g. 4-wire differential signaling) and m=l2, it may be assumed the possible symbol transition per one T, r = 3 (= 2 '™ l ). If the number of symbols in a group, m = 12, a 12-digit ternary number (base-3 number): Tn, Tio, . . . ,T2, Ti, To, where each T,: 0, 1 , 2. For example, for {Tn, Tio, ... T 2 , Ti , T 0 } = {2, 1, 0, 0, 1 , 1 , 0, 1 ,0, 1 , 2, 1 } , the ternary number is:

2100 1 101 01213 (Ternary number)

------ 2 χ 3 ι ι +1 χ 3 , 0 -Κ) χ 3 9 +ί) ; < 3 8 + 1 3 7 +1 χ 3 +0 χ 3 5 +]. χ 3 4

+ 0*3 3 +! : <3 2 -i-2x3 ! +l x3°

- 416356 (0x65A64).

In this manner, 12 transitions numbers may be converted into a number. Note that the transition number 2100 1 101 0121-, may be used as the transition number, such that each integer may be mapped to a sequential symbol and vice versa.

Conversion Between Sequential Symbols and Transition Numbers

082] FIG. 11 illustrates one example 1 100 of conversion between sequential symbols and transition numbers. This conversion maps each transition from a previous sequential symbol number (Ps) to a current sequexitial symbol number (Cs) to a transition xiumber (T). At the transmitter device, the transition symbol numbers are converted to sequential symbol numbers. A relative conversion scheme may be selected to produce transition numbers which guarantee that no two consecutive sequexitial symbols numbers 1104 are the same.

083] The transition diagram 1 104 illustrates an example of a 2 -lane communication interface, using a 4-wire differential signaling system or a 2 -wire single-ended signaling system. In this example, 4 raw symbols may be assigned to 4 sequential symbol numbers SO, SI , S2, and S3. Table 1102 illustrates an example of assignment of a transition number (T) based on a previous sequential symbol number (Ps) and the current sequential symbol number (Cs), in accordance with the transition diagram 1 104. In this example, the transition number T may be assigned according to:

T = Ps+l < Cs

? Cs - (Ps+1 )

: Cs - (Ps+l ) + 4.

Conversely, the current sequential symbol number (Cs) may be assigned according to:

Cs - Ps+1 + T < 4

? Ps+ 1 + T

; Ps 1 + T - 4.

084] A similar approach may be used for an «-lane communication interface by constructing a mapping of sequential symbol number to transition number table for any n (e.g.. «=4, 5, 6, ...) that guarantees that the raw symbols will change at every transition. As noted elsewhere herein, the «-lane communication interface may be implemented using an n- wire single-ended signaling system or a 2«-wire differential signaling system. [0085] For example, in the case of an «-lane communication interface, the transition number T may be assigned according to:

Γ IV ! < Cs

? i s ( Is ! )

: i s s IV 1 } · 2".

[0086] Conversely, in the case of an n-lane communication interface, the cuirent sequential symbol number (Cs) may be assigned according to:

Cs = Ps+l + T < 2"

? IN ! + T

: Ps+l + T - 2".

Utilization Examples

[0087| Depending on the number of lanes and corresponding number of wires/conductors used and the symbols/group selected, different utilization percentages may be achieved. "Utilization" may refer to the efficiency with which a number of bits per group may be sent. In these example, "utilization" may be represented as a percentage between an integer number of bits per group that are transmitted and a theoretical number of bits per group that may be transmitted for a given number of lanes and/or conductors and symbols per group.

[0088| FIG. 12 illustrates a utilization table for a 2 -lane communication interface using ail 3 available states per symbol for various symbols per group. In this example, 1.5833 bits/cycle can be sent by 12 symbols/group, while a i symbol/group can only send 1 bit/cycle.

[0089] FIG. 13 illustrates a utilization table for a 3-iane communication interface using ail 7 available states per symbol for various symbols per group. In this example, 2.791 7 bits/cycle can be sent by 24 symbols/group, while a 1 symbol/group can only send 2 bits/cycle. Note that this results in 67 bits of information being sent (or 99.44% utilization). For example, the 67 bits can be used for 64 data bits and 3 control bits.

[0090] FIG. 14 illustrates a utilization table for a 3-lane communication interface using 6 available states per symbol (after reserving I state for a special purpose) for various symbols per group. In this example, 2.5769 bits/cycle can be sent by 26 symbols/group, while 1 symbol/group can only send 2 bits/cycle. Note that this results in 67 bits of information being sent (or 99.69% utilization).

[00911 Some communication interfaces may not use some states among ail the available symbol states. For example for n=3 the state "1 1 1 " may be reserved for other purposes. n the table in FIG. 14, 1 state has been dumped/reserved from a total of 8 symbol states. The available transition number is then 6 = 2'-2 (i.e., transitions to all states other than self and the reserved/dumped state).

[0092] FIG. 15 illustrates a utilization table for a 4-lane communication interface using all 15 available states per symbol for various symbols per group. In this example, 3.9 bits/cycle can be sent by 10 symbols/group, while 1 symbol/group can only send 3 bits/cycle. Note that this results in 39 bits of information being sent (or 99.82% utilization).

[0093] FIG. 16 illustrates a utilization table for a 4-lane communication interface using 14 available states per symbol (after reserving i state for a special purpose) at various symbols per group. In this example, 3.8 bits/cycle can be sent by 10 symbols/group, while 1 symbol/group can only send 3 bits/cycle. Note that this results in 38 bits of information being sent (or 99.81% utilization).

[0094] Some communication interfaces may not use some states among all the available symbol states. For example for n=4 the state "I 1 1 1 " may be reserved for other purposes. In the table in FIG. 16, 1 state has been dumped from a total of 16 symbol states. The available transition number is then 14 = 2 4 -2 (i.e., transitions to all states other than self and the reserved/dumped state).

[0095] FIG. 17 illustrates a utilization table for a 5 -wire system using all 31 available states per symbol for various symbols per group.

[0096] FIG. 18 illustrates a utilization table for a 5-lane communication interface using 30 available states per symbol (after reserving 1 state for a special puipose) at. various symbols per group.

[0097] FIG. 19 illustrates a utilization table for an 8-lane communication interface using all 255 available states per symbol for various symbols per group.

[0098| FIG. 20 illustrates a utilization table for an 8-3ane communication interface using 254-- available states per symbol (after reserving 1 state for a special puipose) at various symbols per group.

[0099] FIG. 21 is a conceptual diagram 2100 illustrating a simplified example of a hardware implementation for an apparatus employing a processing circuit 2102 that may be configured to perform one or more functions disclosed herein. In accordance with various aspects of the disclosure, an element, or any portion of an element, or any combination of elements as disclosed herein may be implemented, using the processing circuit 2102. The processing circuit 2102 may include one or more processors 2104 that are controlled by some combination of hardware and software modules. Examples of processors 2104 include microprocessors, microcontrollers, digital signal processors (DSPs), field programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, sequencers, gated logic, discrete hardware circuits, and other suitable hardware configured to perform the various functionality described throughout this disclosure. The one or more processors 2104 may include specialized processors that perform specific fuxictions, and that may be configured, augmented or controlled by oxie of the software modules 21 16. The one or more processors 2104 may be configured through a combination of software modules 2116 loaded during initialization, and further configured by loadmg or unloading one or more software modules 21 16 during operation,

[001001 In the illustrated example, the processing circuit 2102 may be implemented with a bus architecture, represented generally by the bus 21 10. The bus 21 10 may include any number of interconnecting buses and bridges depending on the specific application of the processing circuit 2102 and the overall design constraints. The bus 21 10 links together various circuits including the one or more processors 2104, and storage 2106. Storage 2106 may include memory devices and mass storage devices, and may be referred to herein as computer-readable media and/or processor-readable media. The bus 21 10 may also link various other circuits such as timing sources, timers, peripherals, voltage regulators, and power management circuits. A bus interface 2108 may provide an interface between the bus 2110 and one or more transceivers 21 12. A transceiver 21 12 may be provided for each networking technology supported by the processing circuit. In some instances, multiple networking technologies may share some or all of the circuitry or processing modules found in a transceiver 21 12. Each transceiver 21 12 provides a means for communicating with various other apparatus over a transmission medium. Depending upon the nature of the apparatus, a user interface 21 18 (e.g., keypad, display, speaker, microphone, joystick) may also be provided, and may be communicatively coupled to the bus 2110 directly or through the bus interface 2108.

[00101] A processor 2104 may be responsible for managing the bus 21 10 and for general processing that may include the execution of software stored in a computer-readable medium that may include the storage 2106. In this respect, the processing circuit 2102, including the processor 2104, may be used to implement any of the methods, functions and techniques disclosed herein. The storage 2106 may be used for storing data that is manipulated by the processor 2104 when executing software, and the software may be configured to implement any one of the methods disclosed herein.

[00102] One or more processors 2104 in the processing circuit 2102 may execute software.

Software shall be construed broadly to mean instructions, instruction sets, code, code segments, program code, programs, subprograms, software modules, applications, software applications, software packages, routines, subroutines, objects, executables, threads of execution, procedures, functions, algorithms, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. The software may reside in computer-readable form in the storage 2106 or hi an externa] computer readable medium. The external computer-readable medium and/or storage 2106 may include a non-transitory computer-readable medium. A non-transitory computer-readable medium includes, by way of example, a magnetic storage device (e.g., hard disk, floppy disk, magnetic strip), an optical disk (e.g., a compact disc (CD) or a digital versatile disc (DVD)), a smart card, a flash memory device (e.g., a "flash drive," a card, a stick, or a key drive), a random access memory (RAM), a read only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPRQM), an electrically erasable PROM (EEPROM), a register, a removable disk, and any other suitable medium for storing software and/or instructions that may be accessed and read by a computer. The computer-readable medium and/or storage 2106 may also include, by way of example, a carrier wave, a transmission line, and any other suitable medium for transmitting software and/or instructions that may be accessed and read by a computer. Computer-readable medium and/or the storage 2106 may reside in the processing circuit 2102, in the processor 2104, external to the processing circuit 2102, or be distributed across multiple entities including the processing circuit 2102. The computer-readable medium and/or storage 2106 may be embodied in a computer program product. By way of example, a computer program product may include a computer-readable medium in packaging materials. Those skilled in the art will recognize how best to implement the described functionality presented throughout this disclosure depending on the particular application and the overall design constraints imposed on the overall system.

[00103] The storage 2106 may maintain software maintained and/or organized in loadable code segments, modules, applications, programs, etc., which may be referred to herein as software modules 21 16. Each of the software modules 21 16 may include instructions and data that, when installed or loaded on the processing circuit 2102 and executed by the one or more processors 2104, contribute to a run-time image 21 14 that controls the operation of the one or more processors 2104. When executed, certain instructions may cause the processing circuit 2102 to perform functions in accordance with certain methods, algorithms and processes described herein,

[001041 Some of the software modules 21 16 may be loaded during initialization of the processing circuit 2102, and these software modules 2116 may configure the processing circuit 2102 to enable performance of the various functions disclosed herein. For example, some software modules 21 16 may configure internal devices and/or logic circuits 2122 of the processor 2104, and may manage access to external devices such as the transceiver 21 12, the bus interface 2108, the user interface 2118, timers, mathematical coprocessors, and so on. The software modules 21 16 may include a control program and/or an operating system that interacts with interrupt handlers and device drivers, and that controls access to various resources provided by the processing circuit 21 02. The resources may include memory, processing time, access to the transceiver 21 12, the user interface 2118, and so on.

[00105] One or more processors 2104 of the processing circuit 2102 may be multifunctional, whereby some of the software modules 21 16 are loaded and configured to perform different functions or different instances of the same function. The one or more processors 2104 may additionally be adapted to manage background tasks initiated in response to inputs from the user interface 21 18, the transceiver 21 12, and device drivers, for example. To support the performance of multiple functions, the one or more processors 2104 may be configured to provide a multitasking environment, whereby each of a plurality of functions is implemented as a set of tasks serviced, by the one or more processors 21 04 as needed or desired. In one example, the multitasking environment may be implemented using a timesharing program 2120 that passes control of a processor 2104 between different tasks, whereby each task returns control of the one or more processors 2104 to the timesharing program 2120 upon completion of any outstanding operations and/or in response to an input such as an interrupt. When a task has control of the one or more processors 2104, the processing circuit is effectively specialized for the purposes addressed by the function associated, with the controlling task. The timesharing program 2120 may include an operating system, a main loop that transfers control on a round-robin basis, a function that allocates control of the one or more processors 2104 in accordance with a prioritization of the functions, and/or an interrupt driven main loop that responds to external events by providing control of the one or more processors 2104 to a handling function.

[00106] FTG. 22 is a flowchart illustrating a method for data communications that may he performed by a transmitter on a multi-wire differential communications link. The communications link may include a plurality of connectors that carry symbols encoded using a suitable encoding scheme. The connectors may include electrically conductive wires, optical signal conductors, semi-conductive interconnects and so on. The method may be performed, by o e or more processors of an encoder and/or device that interacts with, or houses the encoder.

[00107] At block 2202, data may be received for communication over a communications Jink using differential signaling. In one example, the communications link may be an LVDS communications link.

[00108] At block 2204, the data may be converted to a set of transition numbers.

[00 09] At block 2206, sequences of symbols may be selected using the transition numbers.

[00110] At block 2202, the sequence of symbols may be transmitted, over a plurality of lanes in the communications link. Each symbol may correspond to a signaling state of a plurality of lanes on the communications link. Each pair of consecutive symbols in the sequences of symbols may include two different symbols such that transmitting the two different symbols causes a transition in signaling state of at least one lane in the communications link. The sequence of symbols may be transmitted as a pluralit of signals. Each signal may be transmitted over one of the plurality of lanes.

[0011 ] In one example, clock information is embedded in transitions in signaling state of the plurality of lanes occurring between symbols consecutively transmitted on the communi cations 1 ink.

[00112] In one example, each lane may be implemented using a pair of differential signal wires.

Transmitting the sequence of symbols may include providing a differential signal to each lane. The differential signal may correspond to a bit position hi each symbol of the sequence of symbols. Transmitting the sequence of symbols may include using low voltage differential drivers to transmit the sequence of symbols.

[00113] The sequence of symbols may be transmitted without a transmit clock signal. A clock lane of the communications link may be repurposed to carry a differential signal corresponding to one bit of symbols transmitted on the communications link. In one example, switching logic may be employed, to repurpose the lane, such that a differential transmitter may receive a signal corresponding to a stream of symbols rather than a signal corresponding to a transmit clock.

[00114] FTG. 23 is a diagram 2300 illustrating a simplified example of a hardware implementation for an apparatus employing a processing circuit 2302. The processing circuit typically has a processor 2316 that may include one or more of a microprocessor, microcontroller, digital signal processor, a sequencer and a state machine. The processing circuit 2302 may be implemented with a bus architecture, represented generally by the bus 2320. The bus 2320 may include any number of interconnecting buses and bridges depending on the specific application of the processing circuit 2302 and the overall design constraints. The bus 2320 links together various circuits including one or more processors and/or hardware modules, represented by the processor 2316, the modules or circuits 2304. 2306 and 2308. line interface circuits 2312 configurable to communicate over connectors or wires 2314 and the computer-readable storage m di um 2318. The bus 2320 may also link various other circuits such as timing sources, peripherals, voltage regulators, and power management circuits, which are well known in the art, and therefore, will not be described any further.

[00115] The processor 2316 is responsible for general processing, including the execution of software stored on the computer-readable storage medium 2316. The software, when executed by the processor 2316, causes the processing circuit 2302 to perform the various functions described supra for any particular apparatus. The computer-readable storage medium 2318 may also be used for storing data that is manipulated by the processor 2316 when executing software, including data decoded from symbols transmitted over the connectors 2314, which may be configured as data lanes and clock lanes. The processing circuit 2302 further includes at least one of the modules 2304, 2306 and 2308. The modules 2304, 2306 and 2308 may be software modules running in the processor 2316, resident/stored in the computer readable storage medium 2318, one or more hardware modules coupled to the processor 2316, or some combination thereof. The modules 2304, 2306 and/or 2308 may include microcontroller instructions, state machine configuration parameters, or some combination thereof.

[00116] In one configuration, an apparatus 2300 for wireless communication includes a module and'Or circuit 2304 that is configured to convert data bits into a plurality of transition numbers, and a module and'Or circuit 2306 configured to convert the plurality of transition numbers into a sequence of symbols. [00117] FIG. 24 is a flowchart illustrating a method for data communications on a multi-wire communications link. The communications link may include a plurality of connectors that cany symbols encoded using a suitable encoding scheme. The connectors may include electrically conductive wires, optical signal conductors, semi-co ductive interconnects and so on. The method may be performed by one or more processors of a decoder and/ or device that interacts with, or houses the decoder.

[00 8] At block 2402 a sequence of symbols may be received from a plurality of lanes in a communications link. The sequence of symbols may be encoded in a plurality of differential signals. Each differential signal may be received from a different lane of the communications link. The communications link may employ low voltage differential signaling.

[0011 | At block 2404, a receive clock corresponding to transitions between consecutive symbols in the sequence of symbols may be extracted. Edges of the receive clock may correspond to transitions between symbols in the sequence of symbols.

[00120] At block 2406, a set of transition numbers may be generated. Each transition number may be representative of difference in signaling states of the communications link corresponding to each pair of consecutive sequences of symbols in the sequence of symbols.

[001211 At block 2408, the set of transition numbers may be converted to data. Each pair of consecutive symbols in the sequences of symbols may include two different symbols such the clock includes an edge corresponding to each symbol in the sequence of symbols,

[00122] In one example, the sequence of symbols may be captured using the receive clock. The first convertor may be controlled using the receive clock. The second converter may be controlled using the receive clock.

[001231 FIG. 25 is a diagram 2500 illustrating a simplified example of a hardware implementation for an apparatus employing a processing circuit 2502. The processing circuit typically has a processor 2516 that may include one or more of a microprocessor, microcontroller, digital signal processor, a sequencer and a state machine. The processing circuit 2502 may be implemented with a bus architecture, represented generally by the bus 2520. The bus 2520 may include any number of interconnecting buses and bridges depending on the specific application of the processing circuit 2502 and the overall design constraints. The bus 2520 links together various circuits including one or more processors and/or hardware modules, represented by the processor 2516, the modules or circuiis 2504, 2506 and 2508, line interface circuits 2512 configurable to communicate over connectors or wires 2514 and the computer-readable storage medium 2518. The bus 2520 may also link various other circuits such as timing sources, peripherals, voltage regulators, and. power management circuits, which are well known in the art, and therefore, will not be described any further.

[00124] The processor 2516 is responsible for general processing, including the execution of software stored on the computer-readable storage medium 2516. The software, when executed by the processor 2516, causes the processing circuit 2502 to perform the various functions described supra for any particular apparatus. The computer-readable storage medium 2518 may also be used for storing data that is manipulated by the processor 2516 when executing software, including data decoded from symbols transmitted over the connectors 2514, which may be configured, as data lanes and clock lanes. The processing circuit 2502 further includes at least one of the modules 2504, 2506 and 2508. The modules 2504, 2506 and 2508 may be software modules running in the processor 2516, resident/stored in the computer readable storage medium 2518, one or more hardware modules coupled to the processor 2 16, or some combination thereof. The modules 2504, 2506 and/or 2508 may include microcontroller instructions, state machi e configuration parameters, or some combination thereof.

[00125| In one configuration, the apparatus 2500 for wireless communication includes an interface circuit 2512 that may include a plurality of low voltage differential receivers. The apparatus 2500 may include a module and/or circuit 2504 that is configured to recover a clock from transitions detected, between symbols transmitted on a communications link 2514, a module and/or circuit 2506 configured to manage or perform symbol-to-transition number conversion, a module and/or circuit 251 0 configured to convert transition numbers into data bits.

[00126| One or more of the components, steps, features and/or functions illustrated in the Figures may be rearranged and/or combined into a single component, step, feature or function or embodied in several components, steps, or functions. Additional elements, components, steps, and/or functions may also be added without departing from novel features disclosed, herein. The apparatus, devices, and/or components illustrated in the Figures may be configured to perform one or more of the methods, features, or steps described in the Figures. The novel algorithms described herein may also be efficiently implemented in software and/or embedded in hardware. 00127] Also, it is noted that the embodiments may be described as a process that is depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe the operations as a sequential process, many of the operations can be performed in parallel or concurrently. In addition, the order of the operations may be re-arranged. A process is terminated when its operations are completed. A process may correspond to a method, a function, a procedure, a subroutine, a subprogram, etc. When a process corresponds to a function, its termination corresponds to a return of the function to the calling function or the main function .

00128] Moreover, a storage medium may represent one or more devices for storing data, including read-only memory (ROM), random access memory (RAM), magnetic disk storage mediums, optical storage mediums, flash memory devices and/or other machine readable mediums for storing information. The term "machine readable medium" includes, but is not limited to portable or fixed storage devices, optical storage devices, wireless channels and various other mediums capable of storing, containing or earning instruction(s) and/or data.

00129] Furthermore, embodiments may be implemented by hardware, software, firmware, middleware, microcode, or any combination thereof. When implemented in software, firmware, middleware or microcode, the program code or code segments to perform the necessary tasks may be stored in a machine -readable medium such as a storage medium or other storage(s). A processor may perform the necessary tasks. A code segment may represent a procedure, a function, a subprogram, a program, a routine, a subroutine, a module, a software package, a class, or any combination of instructions, data structures, or program statements. A code segment may be coupled to another code segment or a hardware circuit by passing and/or receiving information, data, arguments, parameters, or memory contents. Information, arguments, parameters, data, etc. may be passed, forwarded, or transmitted via any suitable means including memory sharing, message passing, token passing, network transmission, etc.

00130] The various illustrative logical blocks, modules, circuits, elements, and/or components described, in connection with the examples disclosed herein may be implemented or performed with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic component, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing components, e.g., a combination of a DSP and a microprocessor, a number of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

[00131] The methods or algorithms described in connection with the examples disclosed herein may be embodied directly in hardware, in a software module executable by a processor, or in a combination of both, in the form of processing unit, programming instructions, or other directions, and may be contained in a single device or distributed across multiple devices. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. A storage medium may be coupled to the processor such thai the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor,

[00132] Those of skill in the art would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this inierchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally ixi terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system.

[00133] The various features of the invention described herein can be implemented in different systems without departing from the invention. It should be noted, that the foregoing embodiments are merely examples and are not to be construed as limiting the invention. The description of the embodiments is intended to be illustrative, and not to limit the scope of the claims. As such, the present teachings can be readily applied to other types of apparatuses and. many alternatives, modifications, and variations will be apparent to those skilled, in the art.