Title:
LOW VOLTAGE EEPROM MEMORY ARRAYS WITH ISOLATED WELLS FOR EACH COLUM
Document Type and Number:
WIPO Patent Application WO2005055243
Kind Code:
A3
Abstract:
A non-volatile memory array includes memory cells connected in a common source arrangement and formed in columns of isolated well regions so that Fowler-Nordheim tunneling is used for both write and erase operations of the memory cells. The memory arrays can be formed as NOR arrays or NAND arrays. In one embodiment, the memory array is formed as a byte alterable EEPROM with parallel access. In another embodiment, an insulated gate bipolar transistor (IGBT) is coupled to the memory cells to increase the cell read current of the memory array. When the memory array incorporates IGBTs on the bitlines, the cell read current becomes independent of the wordline voltages. Thus, the memory array of the present invention can be operated at low voltages. The use of IGBTs in the memory array of the present invention enables formation of embedded non-volatile memories in low-voltage digital integrated circuits.
Inventors:
SPADEA GREGORIO (US)
Application Number:
PCT/US2004/039165
Publication Date:
September 22, 2005
Filing Date:
November 22, 2004
Export Citation:
Assignee:
SPADEA GREGORIO (US)
International Classes:
G11C16/04; H01L21/8247; H01L27/115; (IPC1-7): G11C16/04; H01L27/115
Foreign References:
| US6404681B1 | 2002-06-11 | |||
| DE19823733A1 | 1999-12-02 | |||
| US20010000306A1 | 2001-04-19 | |||
| US6649453B1 | 2003-11-18 |
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