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Title:
LSI, FAIL-SAFE LSI FOR RAILWAYS, ELECTRONIC DEVICE, AND ELECTRONIC DEVICE FOR RAILWAYS
Document Type and Number:
WIPO Patent Application WO/2011/081052
Kind Code:
A1
Abstract:
Conventional fail-safe LSIs have been used for the placement of processors and comparators in chips, but have not been used for the placement of package signal pins. The adaptability of fail-safe LSIs to various peripheral circuits and high speed memory has also not been considered. An integrated internal interface, in which the output from two processors is matched, is connected to a common line internal bus, and a plurality of external interface circuits are connected to the common line internal bus. Furthermore, signal pins corresponding to two systems are disposed at opposite corners of a package, and signal pins corresponding to a common line are disposed therebetween.

Inventors:
NAKAMIKAWA TETSUAKI (JP)
SHIMAMURA KOTARO (JP)
SAKUYAMA HIDEO (JP)
TAKEHARA TAKESHI (JP)
Application Number:
PCT/JP2010/072953
Publication Date:
July 07, 2011
Filing Date:
December 21, 2010
Export Citation:
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Assignee:
HITACHI LTD (JP)
NAKAMIKAWA TETSUAKI (JP)
SHIMAMURA KOTARO (JP)
SAKUYAMA HIDEO (JP)
TAKEHARA TAKESHI (JP)
International Classes:
H01L21/822; G06F11/18; G06F15/78; H01L21/82; H01L27/04; H03K19/007
Foreign References:
JP2006031727A2006-02-02
JP2005123591A2005-05-12
JP2002135963A2002-05-10
JP2005049967A2005-02-24
JP2001249701A2001-09-14
JPH07295844A1995-11-10
JPS63271540A1988-11-09
Attorney, Agent or Firm:
Patent Corporate Body Dai-ichi Kokusai Tokkyo Jimusho (JP)
The first international patent firm of a patent business corporation (JP)
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