MAGNETOELECTRIC SPIN ORBIT LOGIC WITH NEGATIVE CAPACITANCE BACKGROUND

[0001] Spintronics is the study of intrinsic spin of the electron and its associated magnetic moment in solid-state devices. Spintronic logic are integrated circuit devices that use a physical variable of magnetization or spin as a computation variable. Such variables can be non-volatile (e.g., preserving a computation state when the power to an integrated circuit is switched off). Non-volatile logic can improve the power and computational efficiency by allowing architects to put a processor to un-powered sleep states more often and therefore reduce energy consumption. Existing spintronic logic generally suffer from high energy and relatively long switching times.

[0002] For example, large write current (e.g., greater than 100 μΑ/bit) and voltage

(e.g., greater than 0.7 V) are needed to switch a magnet (i.e., to write data to the magnet) in Magnetic Tunnel Junctions (MTJs). Existing Magnetic Random Access Memory (MRAM) based on MTJs also suffer from high write error rates (WERs) or low speed switching. For example, to achieve lower WERs, switching time is slowed down which degrades the performance of the MRAM. MTJ based MRAMs also suffer from reliability issues due to tunneling current in the spin filtering tunneling dielectric of the MTJs e.g., magnesium oxide (MgO).

BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The embodiments of the disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure, which, however, should not be taken to limit the disclosure to the specific embodiments, but are for explanation and understanding only.

[0004] Fig. 1A illustrates magnetization response to applied magnetic field for a ferromagnet.

[0005] Fig. IB illustrates magnetization response to applied magnetic field for a paramagnet.

[0006] Fig. 1C illustrates magnetization response to applied voltage field for a paramagnet connected to a magnetoelectric layer.

[0007] Fig. 2Α illustrates a magnetoelectric spin orbit (MESO) logic with negative capacitance for voltage enhancement, according to some embodiments of the disclosure. [0008] Fig. 2B illustrates a spin orbit material stack at the input of an interconnect, according to some embodiments of the disclosure.

[0009] Fig. 2C illustrates a magnetoelectric material stack and series capacitance at the output of an interconnect, according to some embodiments of the disclosure.

[0010] Fig. 2D illustrates a capacitor model of the stack of Fig. 2C, in accordance with some embodiments.

[0011] Fig. 3 illustrates a MESO logic with negative capacitance for voltage enhancement, according to some embodiments of the disclosure.

[0012] Fig. 4A illustrates a MESO logic operable as a repeater, according to some embodiments.

[0013] Fig. 4B illustrates a MESO logic operable as an inverter, according to some embodiments.

[0014] Fig. 5 illustrates a top view of a layout of the MESO logic, according to some embodiments.

[0015] Fig. 6 illustrates a majority gate using MESO logic devices, according to some embodiments.

[0016] Fig. 7 illustrates a top view of a layout of the majority gate of Fig. 6,

according to some embodiments.

[0017] Fig. 8A illustrates an equivalent circuit model of ferroelectric capacitor (FE-

Cap).

[0018] Fig. 8B illustrates a plot showing charge versus voltage characteristics showing the negative capacitance region.

[0019] Fig. 9A illustrates an equivalent circuit model of part of the MESO logic of

Fig. 2A of the magnetoelectric capacitor (with ferroelectric properties) and the series capacitive device, according to some embodiments of the disclosure.

[0020] Fig. 9B illustrates a plot showing a voltage amplification mode from the negative capacitance of the circuit model of Fig. 9B, according to some embodiments of the disclosure.

[0021] Fig. 9C illustrates a plot showing normal mode with no voltage amplification.

[0022] Fig. 10A illustrates an equivalent circuit model for a MESO logic without series coupled capacitive device.

[0023] Fig. 10B illustrates an equivalent circuit model for the MESO logic of Fig. 2A with series coupled capacitive device providing negative capacitance, according to some embodiments of the disclosure. [0024] Fig. 11 illustrates plots showing simulation of MESO logic with resistive shunt path with the equivalent circuit model for the MESO logic, according to some embodiments of the disclosure.

[0025] Figs. 12A-G illustrate plots showing simulation of MESO logic with negative capacitance enhancement of the voltage applied to the ferroelectric, according to some embodiments.

[0026] Fig. 13 illustrates a smart device or a computer system or a SoC (System-on-

Chip) with MESO logic, according to some embodiments.

DETAILED DESCRIPTION

[0027] The Magnetoelectric (ME) effect has the ability to manipulate the magnetization (and the associated spin of electrons in the material) by an applied electric field. Since an estimated energy dissipation per unit area per magnet switching event through the ME effect is an order of magnitude smaller than with spin-transfer torque (STT) effect, ME materials have the capability for next-generation memory and logic applications.

[0028] Various embodiments describe a Magnetoelectric Spin Orbit (MESO) Logic which is a combination of various physical phenomena for spin-to-charge and charge-to-spin conversion, where the MESO logic comprises one or more capacitive devices coupled in series with a magnetoelectric layer of the MESO logic. In some embodiments, the series coupled capacitive device(s) provide negative capacitance based voltage enhancement to a layer coupled to the magnetoelectric layer. As such, the magnetoelectric layer (which includes ferroelectric properties) can be switched faster for faster switching of an associated magnet.

[0029] In some embodiments, spin-to-charge conversion is achieved via one or more layers with the inverse Rashba-Edelstein effect (or inverse spin Hall effect) wherein a spin current injected from an input magnet produces a charge current. The sign of the charge current is determined by the direction of the injected spin and thus of magnetization. In some embodiments, charge-to-spin conversion is achieved via magnetoelectric effect in which the charge current produces a voltage on a capacitor, comprising a layer with magnetoelectric effect, leading to switching magnetization of an output magnet. In various embodiments, this voltage is enhanced by the negative capacitance effect caused by the series coupled capacitive device. In some embodiments, magnetic response of a magnet is according to an applied exchange bias from the magnetoelectric effect, which is enhanced by the negative capacitance effect caused by the series coupled capacitive device. [0030] There are many technical effects of various embodiments. For example, high speed operation of the logic (e.g., 100 picoseconds (ps)) is achieved via the use of magnetoelectric switching operating on semi-insulating nanomagnets. In some examples, switching energy is reduced (e.g., 1-10 attojoules (aJ)) because the current needs to be "on" for a shorter time (e.g., approximately 3 ps) in order to charge the capacitor. In some examples, in contrast to the spin current, here charge current does not attenuate when it flows through an interconnect. As such, the range of interconnects is increased because fewer repeaters may be used. In some embodiments, the voltage enhancement from the series coupled capacitive device (which provides negative capacitance) improves (e.g., speeds up) the ferroelectric switching response time (e.g., switching of the magnetoelectric layer). Other technical effects will be evident from various embodiments and figures.

[0031] In the following description, numerous details are discussed to provide a more thorough explanation of embodiments of the present disclosure. It will be apparent, however, to one skilled in the art, that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring embodiments of the present disclosure.

[0032] Note that in the corresponding drawings of the embodiments, signals are represented with lines. Some lines may be thicker, to indicate more constituent signal paths, and/or have arrows at one or more ends, to indicate primary information flow direction. Such indications are not intended to be limiting. Rather, the lines are used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit or a logical unit. Any represented signal, as dictated by design needs or preferences, may actually comprise one or more signals that may travel in either direction and may be implemented with any suitable type of signal scheme.

[0033] Throughout the specification, and in the claims, the term "connected" means a direct connection, such as electrical, mechanical, or magnetic connection between the things that are connected, without any intermediary devices. The term "coupled" means a direct or indirect connection, such as a direct electrical, mechanical, or magnetic connection between the things that are connected or an indirect connection, through one or more passive or active intermediary devices. The term "circuit" or "module" may refer to one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data/clock signal. The meaning of "a," "an," and "the" include plural references. The meaning of "in" includes "in" and "on."

[0034] The terms "substantially," "close," "approximately," "near," and "about," generally refer to being within +/- 10% of a target value (unless specifically specified). Unless otherwise specified the use of the ordinal adjectives "first," "second," and "third," etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.

[0035] For the purposes of the present disclosure, phrases "A and/or B" and "A or B" mean (A), (B), or (A and B). For the purposes of the present disclosure, the phrase "A, B, and/or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0036] For purposes of the embodiments, the transistors in various circuits and logic blocks described here are metal oxide semiconductor (MOS) transistors or their derivatives, where the MOS transistors include drain, source, gate, and bulk terminals. The transistors and/or the MOS transistor derivatives also include Tri-Gate and FinFET transistors, Gate All Around Cylindrical Transistors, Tunneling FET (TFET), Square Wire, or Rectangular Ribbon Transistors, ferroelectric FET (FeFETs), or other devices implementing transistor functionality like carbon nanotubes or spintronic devices. MOSFET symmetrical source and drain terminals i.e., are identical terminals and are interchangeably used here. A TFET device, on the other hand, has asymmetric Source and Drain terminals. Those skilled in the art will appreciate that other transistors, for example, Bi-polar junction transistors— BJT PNP/NPN, BiCMOS, CMOS, eFET, etc., may be used without departing from the scope of the disclosure. The term "MN" indicates an n-type transistor (e.g., NMOS, NPN BJT, etc.) and the term "MP" indicates a p-type transistor (e.g., PMOS, PNP BJT, etc.).

[0037] Fig. 1A illustrates a magnetization hysteresis plot 100 for ferromagnet 101.

The plot shows magnetization response to applied magnetic field for ferromagnet 101. The x-axis of plot 100 is magnetic field 'FT while the y-axis is magnetization 'm'. For ferromagnet (FM) 101, the relationship between 'FT and 'm' is not linear and results in a hysteresis loop as shown by curves 102 and 103. The maximum and minimum magnetic field regions of the hysteresis loop correspond to saturated magnetization configurations 104 and 106, respectively. In saturated magnetization configurations 104 and 106, FM 101 has stable magnetizations. In the zero magnetic field region 105 of the hysteresis loop, FM 101 does not have a definite value of magnetization, but rather depends on the history of applied magnetic fields. For example, the magnetization of FM 101 in configuration 105 can be either in the +x direction or the -x direction for an in-plane FM. As such, changing or switching the state of FM 101 from one magnetization direction (e.g., configuration 104) to another magnetization direction (e.g., configuration 106) is time consuming resulting in slower nanomagnets response time. It is associated with the intrinsic energy of switching proportional to the area in the graph contained between curves 102 and 103.

[0038] Fig. IB illustrates magnetization plot 120 for paramagnet 121. Plot 120 shows the magnetization response to applied magnetic field for paramagnet 121. The x-axis of plot 120 is magnetic field 'FT while the y-axis is magnetization 'm'. A paramagnet, as opposed to a ferromagnet, exhibits magnetization when a magnetic field is applied to it. Paramagnets generally have magnetic permeability greater or equal to one and hence are attracted to magnetic fields. Compared to plot 100, the magnetic plot 120 of Fig. IB does not exhibit hysteresis which allows for faster switching speeds and smaller switching energies between the two saturated magnetization configurations 124 and 126 of curve 122. In the middle region 125, paramagnet 121 does not have any magnetization because there is no applied magnetic field (e.g., H=0). The intrinsic energy associated with switching is absent in this case.

[0039] Fig. 1C illustrates plot 130 showing magnetization response to applied voltage field for a paramagnet 131 connected to a magnetoelectric layer 132. Here, the x-axis is voltage 'V applied across ME layer 132 and y-axis is magnetization 'm'. Ferroelectric polarization 'PFE' is in ME layer 132 is indicated by an arrow. In this example,

magnetization is driven by exchange bias exerted by a ME effect from ME layer 132. When positive voltage is applied to ME layer 132, paramagnet 131 establishes a deterministic magnetization (e.g., in the +x direction by voltage +V _C ) as shown by configuration 136. When negative voltage is applied by ME layer 132, paramagnet 131 establishes a

deterministic magnetization (e.g., in the -x direction by voltage -V _c ) as shown by

configuration 134. Plot 130 shows that magnetization functions 133a and 133b have hysteresis. In some embodiments, by combining ME layer 132 with paramagnet 131, switching speeds of paramagnet as shown in Fig. IB are achieved. In some embodiments, the hysteresis behavior of FM 131, as shown in Fig. 1C, is associated with the driving force of switching rather than the intrinsic resistance of the magnet to switching.

[0040] Fig. 2A illustrates a MESO logic 200 with negative capacitance for voltage enhancement, according to some embodiments of the disclosure. Fig. 2B illustrates a spin orbit material stack at the input of an interconnect, according to some embodiments of the disclosure. Fig. 2C illustrates a magnetoelectric material stack and series capacitance at the output of an interconnect, according to some embodiments of the disclosure. Fig. 2D illustrates a capacitor model of the stack of Fig. 2C, in accordance with some embodiments. It is pointed out that those elements of Figs. 2A-D having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0041] In some embodiments, MESO logic 200 comprises a first magnet 201, a stack of layers (e.g., layers 202, 203, and 204, also labeled as 202a/b, 203a/b, and 204a/b), interconnecting conductor 205 (e.g., a non-magnetic charge conductor), magnetoelectric (ME) layer 206 (206a/b), second magnet 207, first capacitive device comprising layers 208a, 209a, and 210a; and second capacitive device comprising 208b, 209b, and 210b.

[0042] In some embodiments, first and second magnets 201 and 207, respectively, have in-plane magnetic anisotropy. In some embodiments, first magnet 201 comprises first and second portions, wherein the first portion of first magnet 201 is adjacent to the stack of layers (e.g., layers 202a, 203a, and 204a). In some embodiments, the second portion of first magnet 201 is adjacent to a magnetoelectric material stack or layer 206b. In some embodiments, second magnet 207 comprises first and second portions, wherein the first portion of second magnet 207 is adjacent to the magnetoelectric material stack or layer 206a. In some embodiments, the second portion of second magnet 207 is adjacent to another stack of layers (e.g., layers 202b, 203b, and 204b).

[0043] In some embodiments, conductor 205 (or charge interconnect) is coupled to at least a portion of the stack of layers (e.g., one of layers 202a, 203a, or 204a) and ME layer 206a. For example, conductor 205 is coupled to layer 204a of the stack.

[0044] In some embodiments, the stack of layers (e.g., layers 202a/b, 203a/b, or

204a/b) is to provide an inverse Rashba-Edelstein effect (or inverse spin Hall effect). In some embodiments, the stack of layers provide spin-to-charge conversion where a spin current Is (or spin energy J _s ) is injected from first magnet 201 and charge current I _c is generated by the stack of layers. This charge current I _c is provided to conductor 205 (e.g., charge interconnect). In contrast to spin current, charge current does not attenuate in conductor 205. The direction of the charge current I _c depends on the direction of magnetization of first magnet 201.

[0045] In some embodiments, the charge current I _c charges the capacitor around ME layer 206a and switches its polarization. ME layer 206a exerts exchange bias on second magnet layer 207, and the direction of the exchange bias determines the magnetization of second magnet 207. The same dynamics occurs by ME layer 206b which exerts exchange bias on first magnet 201 according to input charge current on conductor 211a.

[0046] In some embodiments, switching of ME layer 206a is improved or made faster by voltage enhancement to the voltage of conductor 205 via negative capacitance provided by a series coupled capacitive device (also referred to as the first capacitive device). In some embodiments, the first capacitive device comprises layers 208a, 209a, and 210a. In some embodiments, layers 209a and 210a are conductors formed of non-magnetic material. For example, layers 209a and 210a are conductors are formed of same material as conductor 205. In some embodiments, layer 209a is a dielectric (e.g., dielectric oxide layer). Some examples of dielectric include: Teflon, Polyethylene, polyimide, polypropylene, polystyrene, titanium dioxide, strontium titanate, barium strontium titanate, barium titanate, calcium copper titanate, etc. In some embodiments, the first capacitive device is coupled in series with the capacitance provided by ME layer 206a. As such, the first capacitive device provides a negative capacitance which results in voltage amplification on node/conductor 205.

[0047] In this example, the length of first magnet 201 is L _m , the width of conductor

205 is Wc, the length of conductor 205 from the interface of layer 204a to ME layer 206a is Lc, t _c is the thickness of the magnets 201 and 207, and ΪΜΕ is the thickness of ME layer 206a. In some embodiments, conductor 205 comprises a material including one of: Cu, Ag, Al, or Au.

[0048] In some embodiments, the input and output charge conductors (21 la and

211b, respectively) and associated spin-to-charge and charge-to-spin converters are provided. In some embodiments, input charge current Icharge(iN) is provided on interconnect 21 la (e.g., charge interconnect made of same material as interconnect 205). In some embodiments, interconnect 21 la is coupled to first magnet 201 via ME layer 206b. In some embodiments, interconnect 21 la is orthogonal to first magnet 201. For example, interconnect 211a extends in the +x direction while first magnet 201 extends in the -y direction. In some embodiments, Icharge(iN) is converted to corresponding magnetic polarization of 201 by ME layer 206b. The materials for ME layers 206a/b are the same as the materials of ME layer 206.

[0049] In some embodiments, an output interconnect 21 lb is provided to transfer output charge current Icharge(OUT) to another logic or stage. In some embodiments, output interconnect 21 lb is coupled to second magnet 207 via a stack of layers that exhibit spin Hall effect and/or Rashba Edelstein effect. For example, layers 202b, 203b, and 204b are provided as a stack to couple output interconnect 211b with second magnet 207. Material wise, layers 202b, 203b, and 204b are formed of the same material as layers 202a, 203a, and 204a, respectively.

[0050] In some embodiments, a transistor (e.g., p-type transistor MPl) is coupled to first magnet 201. In this example, the source terminal of MPl is coupled to a supply Vdd, the gate terminal of MPl is coupled to a control voltage V _c i (e.g., a switching clock signal, which switches between Vdd and ground), and the drain terminal of MPl is coupled to first magnet 201. In some embodiments, a contact (not shown) made of any suitable conducting material is used to connect the transistor to the first magnet 201. In some embodiments, the current Idrive from transistor MPl generates spin current into the stack of layers (e.g., layers 202a, 203 a, and 204a).

[0051] In some embodiments, along with the p-type transistor MP l connected to Vdd

(or an n-type transistor connected to Vdd but with gate overdrive above Vdd), an n-type transistor MN1 is provided which couples to first magnet 201 , where the n-type transistor is operable to couple ground (or 0 V) to first magnet 201. In some embodiments, n-type transistor MN2 is provided which is operable to couple ground (or 0V) to second magnet 207.

[0052] In some embodiments, p-type transistor MP2 is provided which is operable to couple power supply (Vdd or -Vdd) to second magnet 207. For example, when clock is low (e.g., Vci=0 V), then transistor MP l is on and Vdd is coupled to first magnet 201 (e.g., power supply is Vdd) and 0 V is coupled to second magnet 207. This provides a potential difference for charge current to flow. Continuing with this example, when clock is high (e.g., Vd=Vdd and power supply is Vdd), then transistor MP l is off, transistor MN1 is on, and transistor MN2 is off. As such, 0 V is coupled to first magnet 201.

[0053] In some embodiments, the power supply is a negative power supply (e.g., -

Vdd). In that case, then the source of transistor MPl is connected to 0 V, and transistor MNl 's source is connected to -Vdd, and transistor MN2 is on. When Vd = 0 V and power supply is -Vdd , then transistor MN1 is on, and transistor MPl is off, and transistor MN2 (whose source is at -Vdd ) is off and transistor MP2 whose source is 0 V is on. In this case, - Vdd is coupled to input magnet 201 and 0 V is coupled to output magnet 207. This also provides a path for charge current to flow. Continuing with this example, when clock is high (e.g., Vd=-Vdd and power supply is -Vdd), then transistor MP l is off, transistor MN1 is on, and transistor MN2 is off. As such, 0 V is coupled to input magnet 201.

[0054] In some embodiments, ME layer 206a/b forms the magnetoelectric capacitor to switch the magnets 201/207. For example, the conductor 205 forms one plate of the capacitor, magnet 207 forms the other plate of the capacitor, and layer 206a is the magnetic- electric oxide that provides out-of-plane exchange bias to second magnet 207. In some embodiments, the magnetoelectric oxide comprises perpendicular exchange bias due to partially compensated anti-ferromagnetism.

[0055] In some embodiments, the first and second capacitive devices coupled to ME layers 206a/b via conductors 205 and 21 la, respectively, provide voltage boost or amplification to the voltage on conductors 205 and 21 la, respectively, carrying charge current. This voltage boost speeds up the charging of the respective magnetoelectric capacitors (also referred to as ferroelectric capacitors or FE-Caps because of the ferroelectric properties in magnetoelectric material). As such, magnets 201 and 207 can be switched faster than without such associated capacitive devices, in accordance with some embodiments.

[0056] In some embodiments, first magnet 201 injects a spin polarized current into the high spin-orbit coupling (SOC) material stack (e.g., layers 202a, 203a, and 204a). The spin polarization is determined by the magnetization of first magnet 201.

[0057] In some embodiments, the stack comprises i) an interface 203a/b with a high density 2D (two dimensional) electron gas and with high SOC formed between 202a/b and 204a/b materials such as Ag or Bi, or ii) a bulk material 204 with high Spin Hall Effect (SHE) coefficient such as Ta, W, or Pt. In some embodiments, a spacer (or template layer) is formed between first magnet 201 and the injection stack. In some embodiments, this spacer is a templating metal layer which provides a template for forming first magnet 201. In some embodiments, the metal of the spacer which is directly coupled to first magnet 201 is a noble metal (e.g., Ag, Cu, or Au) doped with other elements from Group 4d and/or 5d of the Periodic Table. In some embodiments, first magnet 201 (and by extension first semi- insulating magnet 209a) are sufficiently lattice matched to Ag (e.g., a material which is engineered to have a lattice constant close (e.g., within 3%) to that of Ag).

[0058] Here, sufficiently matched atomistic crystalline layers refer to matching of the lattice constant 'a' within a threshold level above which atoms exhibit dislocation which is harmful to the device (for instance, the number and character of dislocations lead to a significant (e.g., greater than 10%) probability of spin flip while an electron traverses the interface layer). For example, the threshold level is within 5% (e.g., threshold levels in the range of 0% to 5% of the relative difference of the lattice constants). As the matching improves (e.g., matching gets closer to perfect matching), spin injection efficiency from spin transfer from first magnet 201 to first ISHE/ISOC stacked layer increases. Poor matching (e.g., matching worse than 5%) implies dislocation of atoms that is harmful for the device. [0059] Table 1 summarizes transduction mechanisms for converting magnetization to charge current and charge current to magnetization for bulk materials and interfaces.

Table 1: Transduction mechanisms for Spin to Charge and Charge to Spin Conversion

[0060] The following section describes the spin to charge and charge to spin dynamics. In some embodiments, the spin-orbit mechanism responsible for spin-to-charge conversion is described by the inverse Rashba-Edelstein effect in 2D electron gases. The Hamiltonian (energy) of spin-orbit coupling electrons in a 2D electron gas is:

H _R = a _R (kxz). σ

where a _R is the Rashba-Edelstein coefficient, 'k' is the operator of momentum of electrons, z is a unit vector perpendicular to the 2D electron gas, and σ is the operator of spin of electrons.

[0061] The spin polarized electrons with direction of polarization in-plane (e.g., in the xy -plane) experience an effective magnetic field dependent on the spin direction:

a _R .

B(k)=— (fcxz)

where i _B is the Bohr magneton

[0062] This results in the generation of a charge current h in interconnect 205 proportional to the spin current (or J _s ). The spin-orbit interaction by Ag and Bi interface layers 202 and 204 (e.g., the Inverse Rashba-Edelstein Effect (IREE)) produces a charge current h in the horizontal direction given as:

. _ ^ _IREE I _S

W _m

where w _m is width of the input magnet 201, and _IREE is the IREE constant (with units of length) proportional to a _R .

[0063] Alternatively, the Inverse Spin Hall Effect in Ta, W, or Pt layer 203a/b produces the horizontal charge current I _c given as:

2w _m

[0064] Both IREE and ISHE effects produce spin-to-charge current conversion around 0.1 with existing materials at 10 nm (nanometers) magnet width. For scaled nanomagnets (e.g., 5 nm wide magnets) and exploratory SHE materials such as Bi2Se3, the spin-to-charge conversion efficiency can be between 1 and 2.5. The net conversion of the drive charge current Idnve to magnetization dependent charge current is given as:

j _± REEP _{for IREE md I} + OsHEtsHEPIs _foj . _j g _jj g

w _m 2w _m

where 'P' is the dimensionless spin polarization. For this estimate, the drive current Idnve and the charge current I _c = I _d = 100 μΑ is set. As such, when estimating the resistance of the ISHE interface to be equal to R = 100 Ω, then the induced voltage is equal to V _ISHE = 10 mV.

[0065] The charge current I _c , carried by interconnect 205, produces a voltage on the capacitor of ME layer 206a comprising magnetoelectric material dielectric (such as BiFeC (BFO) or CnCb) in contact with second magnet 207 (which serves as one of the plates of the capacitor) and interconnect 205 (which series as the other of the plates of the capacitor). In some embodiments, magnetoelectric materials are either intrinsic multiferroic or composite multiferroic structures. As the charge accumulates on the magnetoelectric capacitor of ME layer 206a, a strong magnetoelectric interaction causes the switching of magnetization in second magnet 207. This magnetoelectric interaction is further enhanced or strengthened by voltage amplification caused by capacitive device comprising layers 208a/b, 209a/b, and 210a/b. These capacitive devices are coupled in series with associated magnetoelectric capacitors, and as such provide negative capacitive effects. The negative capacitive effects result in voltage amplification on conductors 205/211 a, and this voltage amplification enhances or speeds up the magnetoelectric interaction which causes faster switching of magnetization of magnets 201/207.

[0066] For the following parameters of the magnetoelectric capacitor: thickness

^ME ⁼ 5 nm, dielectric constant ε = 500, area A = 60 nm x 20 nm. Then the capacitance is given as:

εε ₀ Α

^C ME =— ^¾ ^fP

^L ME

[0067] Demonstrated values of the magnetoelectric coefficient is a _ME ~10/c , where the speed of light is c. This translates to the effective magnetic field exerted on second semi- insulating magnet 207, which is expressed as:

BME = a _ME E = -0.06Γ

This is a strong field sufficient to switch magnetization. [0068] The charge on the capacitor of ME layer 206a is Q =— x lO mV = 10 aC, and the time to fully charge it to the induced voltage is td = 10— ~ 1 ps (with the account of decreased voltage difference as the capacitor charges). If the driving voltage is V _d = 100 mV, then the energy E _sw to switch is expressed as:

which is comparable to the switching energy of CMOS transistors. Note that the time to switch t _sw magnetization remains much longer than the charging time and is determined by the magnetization precession rate. The micro-magnetic simulations predict this time to be t _sw ~100ps, for example.

[0069] The negative capacitance ^(See Fig. 2D) provided by capacitor comprising layers 208a, 209a, and 210a can be expressed follows:

where 'A' is the area of the capacitive plate (e.g., area of layer 208a assuming surface area of layers 209a and 210a are the same as surface area of layer 208a), 'd' is the thickness of the dielectric layer 209a, 'P' is the polarization, and Έ' is the electric field.

[0070] A voltage division caused by the two series coupled capacitors CME and Ci results in voltage amplification on conductor 205 when Ci is substituted with a capacitor having a negative capacitance.

[0071] In some embodiments, materials for first and second magnets 201 and 207 have saturated magnetization M _s and effective anisotropy field Hk. Saturated magnetization Ms is generally the state reached when an increase in applied external magnetic field H cannot increase the magnetization of the material. Anisotropy Hk generally refers material properties that are highly directionally dependent.

[0072] In some embodiments, materials for first and second magnets 201 and 207, respectively, are non-ferromagnetic elements with strong paramagnetism which have high number of unpaired spins but are not room temperature ferromagnets. A paramagnet, as opposed to a ferromagnet, exhibits magnetization when a magnetic field is applied to it. Paramagnets generally have magnetic permeability greater or equal to one and hence are attracted to magnetic fields. In some embodiments, magnets 209a/b and 210a/b comprise a material which includes one or more of: Platinum(Pt), Palladium (Pd), Tungsten (W), Cerium (Ce), Aluminum (Al), Lithium (Li), Magnesium (Mg), Sodium (Na), CnC (chromium oxide), CoO (cobalt oxide), Dysprosium (Dy), Dy20 (dysprosium oxide), Erbium (Er), En03 (Erbium oxide), Europium (Eu), EU2O3 (Europium oxide), Gadolinium (Gd), Gadolinium oxide (Gd2Cb), FeO and Fe2Cb (Iron oxide), Neodymium (Nd), Nd2Cb (Neodymium oxide), KO2 (potassium superoxide), praseodymium (Pr), Samarium (Sm), SrmC (samarium oxide), Terbium (Tb), Τ¾θ3 (Terbium oxide), Thulium (Tm), TrraCb (Thulium oxide), and V2O3 (Vanadium oxide). In some embodiments, the first and second paramagnets 201 and 207 comprise dopants selected from a group which includes one or more of: Ce, Cr, Mn, Nb, Mo, Tc, Re, Nd, Gd, Tb, Dy, Ho, Er, Tm, and Yb.

[0073] In some embodiments, first and second magnets 201 and 207, respectively, are ferromagnets. In some embodiments, first and second magnets 201 and 207, respectively, comprise one or a combination of materials which includes one or more of: a Heusler alloy, Co, Fe, Ni, Gd, B, Ge, Ga, permalloy, or Yttrium Iron Garnet (YIG), and wherein the Heusler alloy is a material which includes one or more of: Cu, Mn, Al, In, Sn, Ni, Sb, Ga, Co, Fe, Si, Pd, Sb, V, Ru, Cu ₂ MnAl, Cu ₂ MnIn, Cu ₂ MnSn, Ni ₂ MnAl, Ni ₂ MnIn, Ni ₂ MnSn, Ni ₂ MnSb, Ni ₂ MnGa Co ₂ MnAl, Co ₂ MnSi, Co ₂ MnGa, Co ₂ MnGe, Pd ₂ MnAl, Pd ₂ MnIn, Pd ₂ MnSn, Pd ₂ MnSb, Co ₂ FeSi, Co ₂ FeAl, Fe ₂ VAl, Mn ₂ VGa, Co ₂ FeGe, MnGa, MnGaRu, or Mn ₃ X, where 'X' is one of Ga or Ge.

[0074] In some embodiments, the stack of layers providing spin orbit coupling comprises: a first layer 202a/b comprising Ag, wherein the first layer is adjacent to first magnet 209a/b; and a second layer 204a/b comprising Bi or W, wherein second layer 204a/b is adjacent to first layer 202a/b and to a conductor (e.g., 205, 21 lb). In some embodiments, a third layer 203a/b (having material which is one or more of Ta, W, or Pt) is sandwiched between first layer 202a/b and second layer 204a/b as shown. In some embodiments, the stack of layers comprises a material which includes one of: β-Ta, β-W, W, Pt, Cu doped with Iridium, Cu doped with Bismuth, or Cu doped an element of 3d, 4d, 5d, 4f, or 5f of periodic table groups.

[0075] In some embodiments, ME layer 206a/b is formed of a material which includes one of: CnC and multiferroic material. In some embodiments, ME layer 206 comprises Cr and O. In some embodiments, the multiferroic material comprises BFO (e.g., BiFeC ), LFO (LuFeC , LuFe204), or La doped BiFeC . In some embodiments, the multiferroic material includes one of: Bi, Fe, O, Lu, or La. In some embodiments, ME layer 206a/b comprises one of: dielectric, para-electric, or ferro-electric material.

[0076] Fig. 3 illustrates a MESO logic 300 with negative capacitance for voltage enhancement, according to some embodiments of the disclosure. It is pointed out that those elements of Fig. 3 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. MESO logic 300 is similar to MESO logic 200 but for an additional capacitive device coupled in series with the magnetoelectric capacitor.

[0077] In some embodiments, MESO logic 300 comprises a third capacitive device

(e.g., d which is in series with CME and Ci) including layer 212a. In some embodiments, layer 212a is adjacent to conductor 205 such that it is between magnetoelectric layer 206a and conductor 205. In some embodiments, layer 212a comprises dielectric material which may be the same material as material for layer 209a. In some embodiments, MESO logic 300 comprises fourth capacitive device including layer 212b. In some embodiments, layer 212b is adjacent to conductor 21 la such that it is between magnetoelectric layer 206b and conductor 21 la. In some embodiments, layer 212b comprises dielectric material which may be the same material as material for layer 209a. Functionally, MESO logic 300 is similar to MESO logic 200. In some embodiments, capacitor d allows for a different design point. In some embodiments, capacitor C2 reverses the logic state.

[0078] Fig. 4A illustrates MESO logic 400 operable as a repeater (or buffer), according to some embodiments. It is pointed out that those elements of Fig. 4B having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. In some embodiments, to configure MESO logic 200 as a repeater, a portion of the stack of the layers (e.g., layer 204a/b) is coupled to ground, first magnet 201 is coupled to a negative supply (e.g., -Vdd), and second magnet 207 is coupled to ground (e.g., 0 V). In some embodiment, the clocking signals, Vd and Vci_t>, enable operation of stages of MESO logic 400

consecutively. For example, in one of the clocking stages, magnet 201 is coupled to Vdd via high conductance in transistor MP1 while magnet 207 is coupled to ground high conductance in transistor MN2.

[0079] In some embodiments, for repeater MESO logic 400, the magnetization direction of first magnet 201 is the same as the magnetization direction of second magnet 207. For example, the magnetization direction of first magnet 201 is in the +y direction while the magnetization direction of second magnet 207 is also in the +y direction. Just like MESO logic 200 is configured as a repeater, MESO logic 300 can also be configured as a repeater using the same biasing technique used for MESO logic 400, in accordance with some embodiments.

[0080] Fig. 4B illustrates MESO logic 420 operable as an inverter, according to some embodiments. It is pointed out that those elements of Fig. 4B having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. In some embodiments, to configure the MESO logic 200 as an inverter, a portion of the stack of the layers (e.g., layer 204a/b) is coupled to ground, first magnet 201 is coupled to a positive supply (e.g., +Vdd), and second magnet 207 is coupled to ground (e.g., 0V).

[0081] In some embodiment, the clocking signals, Vd and V _c i_b, enable operation of stages of MESO logic 420 consecutively. For example, in one of the clocking stages, magnet 201 is coupled to Vdd via high conductance in transistor MP1 while magnet 207 is coupled to ground high conductance in transistor MN2.

[0082] In some embodiments, for inverter MESO 420, the magnetization direction of first magnet 201 is opposite compared to the magnetization direction of second magnet 207. For example, the magnetization direction of first magnet 201 is in the -y direction while the magnetization direction of second magnet 207 is in the +y direction. Just like MESO logic 200 is configured as an inverter, MESO logic 300 can also be configured as an inverter using the same biasing technique used for MESO logic 420, in accordance with some

embodiments.

[0083] MESO logic devices of various embodiments provide logic cascadability and unidirectional signal propagation (e.g., input-output isolation). The unidirectional nature of logic is ensured due to large difference in impedance for injection path versus detection path, in accordance with some embodiments. In some embodiments, the injector is essentially a metallic spin valve with spin to charge transduction with RA (resistance area) products of approximately 10 mOhrarnicron ² . In some embodiments, the detection path is a low leakage capacitance with RA products much larger than 1 MOhm. micron ² in series with the resistance of the FM capacitor plate with estimated resistance greater than 500 Ohms.

[0084] Fig. 5 illustrates a top view of layout 500 of MESO logic 200, according to some embodiments. An integration scheme for MESO devices with CMOS drivers for power supply and clocking is shown in the top view. Here, transistor MP1 is formed in the active region 501, and power supply is provided via metal layer 3 (M3) indicated as 506. The gate terminal 504 of transistor MP1 is coupled to a supply interconnect 505 through via or contact 503. In some embodiments, M3 layer 507 is coupled to ground which provides ground supply to layer 204. In some embodiments, another transistor can be formed in active region 503 with gate terminal 510. Here, 508 and 509 are contact vias coupled to power supply line. In some embodiments, the density of integration of the devices exceeds that of CMOS since an inverter operation can be achieved within 2.5P x 2M0. In some embodiments, since the power transistor MP1 can be shared among all the devices at the same clock phases, vertical integration can also be used to increase the logic density as described with reference to Fig. 6, in accordance with some embodiments.

[0085] Fig. 6 illustrates majority gate 600 using MESO logic devices, according to some embodiments. It is pointed out that those elements of Fig. 6 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. A charge mediated majority gate is proposed using the spin orbit coupling and magnetoelectric switching. A charge mediated majority gate is shown in Fig. 6.

[0086] Majority gate 600 comprises at least three input stages 601, 602, and 603 with their respective charge conductors 2051, 2052, and 2053 coupled to summing interconnect 604. In some embodiments, summing interconnect 604 is made of the same materials as interconnect 205. In some embodiments, summing interconnect 604 is coupled to output stage 605 which includes the second magnet 507 (like 207). The three input stages 601, 602, and 603 share a common power/clock region therefore the power/clock gating transistor can be shared among the three inputs of the majority gate, in accordance with some embodiments. The input stages 601, 602, and 603 can also be stacked vertically to improve the logic density, in accordance with some embodiments. The charge current at the output (Icharge(OUT)) is the sum of currents I _C hi, , and I _C h3.

[0087] Fig. 7 illustrates a top view of layout 700 of the majority gate, according to some embodiments. It is pointed out that those elements of Fig. 7 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. Majority gate 700 comprises at least three input stages 601/701, 602/702, and 603/703 with their respective conductors 205i, 2052, and 2053 coupled to summing interconnect 604/702.

[0088] Fig. 8A illustrates an equivalent circuit model 800 of a ferroelectric capacitor

(FE-Cap) based on the Landau Khanlatnikov (LK) model. Fig. 8B illustrates plot 820 showing charge versus voltage characteristics showing the negative capacitance region.

Model 800 illustrates a circuit that provides ferroelectric voltage VFE and comprises capacitor CO in parallel with a series coupled resistance pO and internal capacitance CF(QF) that provides internal voltage Vint. Plot 820 shows the capacitance behavior of a ferroelectric capacitor when connected with a load capacitor. Here, x-axis is the internal voltage Vint in volts, while the y-axis is charge from the ferroelectric capacitor when connected with a load capacitor. Here, the dotted region 821 represents the negative capacitance region between the coercive voltage bounds.

[0089] When a voltage source drives the FE-Cap connected with a load capacitor, the operating region of a FE-cap is biased by the load capacitance. When the FE-Cap is biased at the negative capacitance region 821 (e.g., charge on FE-cap is positive while the voltage across the FE-cap is negative, and vice versa), the voltage across the load capacitance can be higher than the input voltage, owning to the ferroelectric polarity charge induced voltage amplification effect. On the other hand, when the FE-Cap is biased at the positive capacitance region, it operates as a regular capacitor. The negative capacitance effect has been mainly utilized for transistor gate stack enhancement (e.g., negative capacitance FETs) for low-voltage transistors. Various embodiments use the concept of negative capacitance to a MESO logic to enhance the switching of magnets via the magnetoelectric layer.

[0090] Fig. 9A illustrates an equivalent circuit model 900 of part of the MESO logic

200 of Fig. 2A of the magnetoelectric capacitor (with ferroelectric properties) and the series capacitive device, according to some embodiments of the disclosure. Fig. 9B illustrates a plot 920 showing a voltage amplification mode from the negative capacitance of the circuit model of Fig. 9B, according to some embodiments of the disclosure. Fig. 9C illustrates plot 930 showing normal mode with no voltage amplification. It is pointed out that those elements of Figs. 9A-C having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0091] Model 900 is same as that disclosed in Fig. 2D, but for a DC source 901 which couples to magnetoelectric capacitor CME (e.g., layers 205a, 206a, and 207a) and load capacitor Ci (e.g., first capacitive device comprises layers 208a, 209a, 210a). When voltage source 901 drives the magnetoelectric capacitor CME connected with a load capacitor Ci, the operating region of the magnetoelectric capacitor CME is biased by the load capacitance Ci. When the magnetoelectric capacitor CME is biased at the negative capacitance region (e.g., region 821 of Fig. 8B), the voltage across the load capacitance Ci becomes higher than the input voltage, owning to the ferroelectric polarity charge induced voltage amplification effect. For instance, when charge on FE-cap is positive while the voltage across the FE-cap is negative, and vice versa, the voltage across the load capacitance Ci becomes higher than the input voltage. This amplification is illustrated by plot 920, which illustrates voltage on nodes (a) and (b), which is the same as node 205 or conductor 205. On the other hand, when the FE-Cap (e.g., magnetoelectric capacitor CME) is biased at the positive capacitance region, it operates as a regular capacitor as illustrated by plot 930 where there is no amplification.

[0092] Fig. 10A illustrates an equivalent circuit model 1000 for a MESO logic without series coupled capacitive device. In this example, resistance 1001 (P ) corresponds to the path from layer 204a to the ground. Circuit model 800 includes transistor MP1 controlled by clock signal Vci, where I _c is the input charge current. Here, resistor 1002 and current controlled current source 1003 are used to model spin-to-charge conversion in layers 202a, 203a, and 204a which senses the current from transistor MP1 passing through magnet 201, resistor 1004 is used to model conductor 205, and capacitor CME 1005 is used to model ME layer 206a. The similar layers 207, 202b, 203b, 204b, 206b, 211 are represented by the corresponding circuit elements in the next stage of the circuit having the same circuit schematic.

[0093] Fig. 10B illustrates an equivalent circuit model 1020 for the MESO logic 200 of Fig. 2A with series coupled capacitive device providing negative capacitance, according to some embodiments of the disclosure. Circuit model 1020 is similar to schematic 1000, but additionally includes capacitor Ci 1026 (to model first capacitve device) coupled in series with magnetoelectric capacitor CME 1025.

[0094] Fig. 11 illustrates plots 1100, 1120, and 1130, respectively, showing simulation of MESO logic with resistive shunt path with the equivalent circuit model for the MESO logic, according to some embodiments of the disclosure. Plot 1100 illustrates leakage current through transistor MP1 overtime, plot 1120 illustrates current through conductor 205 (also referred to interconnect current), and plot 1130 illustrates leakage current though resistor 1001. Plot 1100 shows the presence of continuous leakage current in the MESO logic. There is continuous leakage path when a shunt resistor is used for driving the spin-to- charge conversion module (e.g., layers 202a, 203a, and 204a). Plots 1120 and 1130 show the operation of the ME device with the current dynamics. Plot 1120 shows that the interconnect current does not change. Plot 1130 shows that leakage through the ground path reduces at higher ground resistance without impactive the operation of the device.

[0095] Figs. 12A-G illustrate plots 1200, 1220, 1230, 1240, 1250, 1260, and 1270 respectively, showing simulation of MESO logic with negative capacitance enhancement of the voltage applied to the ferroelectric, according to some embodiments. Plot 1200 illustrates toggling Vci received at the gate of transistor MP1. Plot 1220 illustrates the ferroelectric voltage across magnetoelectric capacitor CME for different values of resistance P , as the gate voltage to transistor MP1 toggles. Plot 1230 illustrates voltage across transistor MP1. Plot 1240 illustrates current through conductor 205 as the gate voltage to transistor MPl toggles. Plot 1250 illustrates current through transistor MPl for various values of resistance P , as the gate voltage to transistor MPl toggles. Plot 1260 illustrates the charge in magnetoelectric capacitor CME as it toggles between retention charge level and the amplified or enhanced charge level caused by negative capacitance from capacitor Ci. Plot 1270 illustrates charge in magnetoelectric capacitor CME over internal voltage Vint of magnetoelectric layer 206a. Plot 1270 shows the charge of the ferroelectric exhibiting the transition through the negative capacitance state.

[0096] Fig. 13 illustrates a smart device or a computer system or a SoC (System-on-

Chip) with MESO logic, according to some embodiments. It is pointed out that those elements of Fig. 13 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0097] Fig. 13 illustrates a block diagram of an embodiment of a mobile device in which flat surface interface connectors could be used. In some embodiments, computing device 1600 represents a mobile computing device, such as a computing tablet, a mobile phone or smart-phone, a wireless-enabled e-reader, or other wireless mobile device. It will be understood that certain components are shown generally, and not all components of such a device are shown in computing device 1600.

[0098] In some embodiments, computing device 1600 includes first processor 1610 with MESO logic, according to some embodiments discussed. Other blocks of the computing device 1600 may also include a MESO logic, according to some embodiments. The various embodiments of the present disclosure may also comprise a network interface within 1670 such as a wireless interface so that a system embodiment may be incorporated into a wireless device, for example, cell phone or personal digital assistant.

[0099] In some embodiments, processor 1610 can include one or more physical devices, such as microprocessors, application processors, microcontrollers, programmable logic devices, or other processing means. The processing operations performed by processor 1610 include the execution of an operating platform or operating system on which applications and/or device functions are executed. The processing operations include operations related to I/O (input/output) with a human user or with other devices, operations related to power management, and/or operations related to connecting the computing device 1600 to another device. The processing operations may also include operations related to audio I/O and/or display I/O. [00100] In some embodiments, computing device 1600 includes audio subsystem

1620, which represents hardware (e.g., audio hardware and audio circuits) and software (e.g., drivers, codecs) components associated with providing audio functions to the computing device. Audio functions can include speaker and/or headphone output, as well as microphone input. Devices for such functions can be integrated into computing device 1600, or connected to the computing device 1600. In one embodiment, a user interacts with the computing device 1600 by providing audio commands that are received and processed by processor 1610.

[00101] In some embodiments, computing device 1600 comprises display subsystem

1630. Display subsystem 1630 represents hardware (e.g., display devices) and software (e.g., drivers) components that provide a visual and/or tactile display for a user to interact with the computing device 1600. Display subsystem 1630 includes display interface 1632, which includes the particular screen or hardware device used to provide a display to a user. In one embodiment, display interface 1632 includes logic separate from processor 1610 to perform at least some processing related to the display. In one embodiment, display subsystem 1630 includes a touch screen (or touch pad) device that provides both output and input to a user.

[00102] In some embodiments, computing device 1600 comprises I/O controller 1640.

I/O controller 1640 represents hardware devices and software components related to interaction with a user. I/O controller 1640 is operable to manage hardware that is part of audio subsystem 1620 and/or display subsystem 1630. Additionally, I/O controller 1640 illustrates a connection point for additional devices that connect to computing device 1600 through which a user might interact with the system. For example, devices that can be attached to the computing device 1600 might include microphone devices, speaker or stereo systems, video systems or other display devices, keyboard or keypad devices, or other I/O devices for use with specific applications such as card readers or other devices.

[00103] As mentioned above, I/O controller 1640 can interact with audio subsystem

1620 and/or display subsystem 1630. For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of the computing device 1600. Additionally, audio output can be provided instead of, or in addition to display output. In another example, if display subsystem 1630 includes a touch screen, the display device also acts as an input device, which can be at least partially managed by I/O controller 1640. There can also be additional buttons or switches on the computing device 1600 to provide I/O functions managed by I/O controller 1640. [00104] In some embodiments, I/O controller 1640 manages devices such as accelerometers, cameras, light sensors or other environmental sensors, or other hardware that can be included in the computing device 1600. The input can be part of direct user interaction, as well as providing environmental input to the system to influence its operations (such as filtering for noise, adjusting displays for brightness detection, applying a flash for a camera, or other features).

[00105] In some embodiments, computing device 1600 includes power management

1650 that manages battery power usage, charging of the battery, and features related to power saving operation. Memory subsystem 1660 includes memory devices for storing information in computing device 1600. Memory can include nonvolatile (state does not change if power to the memory device is interrupted) and/or volatile (state is indeterminate if power to the memory device is interrupted) memory devices. Memory subsystem 1660 can store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of the applications and functions of the computing device 1600.

[00106] Elements of embodiments are also provided as a machine-readable medium (e.g., memory 1660) for storing the computer-executable instructions (e.g., instructions to implement any other processes discussed herein). The machine-readable medium (e.g., memory 1660) may include, but is not limited to, flash memory, optical disks, CD-ROMs, DVD ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, phase change memory (PCM), or other types of machine-readable media suitable for storing electronic or computer- executable instructions. For example, embodiments of the disclosure may be downloaded as a computer program (e.g., BIOS) which may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals via a communication link (e.g., a modem or network connection).

[00107] In some embodiments, computing device 1600 comprises connectivity 1670.

Connectivity 1670 includes hardware devices (e.g., wireless and/or wired connectors and communication hardware) and software components (e.g., drivers, protocol stacks) to enable the computing device 1600 to communicate with external devices. The computing device 1600 could be separate devices, such as other computing devices, wireless access points or base stations, as well as peripherals such as headsets, printers, or other devices.

[00108] Connectivity 1670 can include multiple different types of connectivity. To generalize, the computing device 1600 is illustrated with cellular connectivity 1672 and wireless connectivity 1674. Cellular connectivity 1672 refers generally to cellular network connectivity provided by wireless carriers, such as provided via GSM (global system for mobile communications) or variations or derivatives, CDMA (code division multiple access) or variations or derivatives, TDM (time division multiplexing) or variations or derivatives, or other cellular service standards. Wireless connectivity (or wireless interface) 1674 refers to wireless connectivity that is not cellular, and can include personal area networks (such as Bluetooth, Near Field, etc.), local area networks (such as Wi-Fi), and/or wide area networks (such as WiMax), or other wireless communication.

[00109] In some embodiments, computing device 1600 comprises peripheral connections 1680. Peripheral connections 1680 include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) to make peripheral connections. It will be understood that the computing device 1600 could both be a peripheral device ("to" 1682) to other computing devices, as well as have peripheral devices ("from" 1684) connected to it. The computing device 1600 commonly has a "docking" connector to connect to other computing devices for purposes such as managing (e.g., downloading and/or uploading, changing, synchronizing) content on computing device 1600. Additionally, a docking connector can allow computing device 1600 to connect to certain peripherals that allow the computing device 1600 to control content output, for example, to audiovisual or other systems.

[00110] In addition to a proprietary docking connector or other proprietary connection hardware, the computing device 1600 can make peripheral connections 1680 via common or standards-based connectors. Common types can include a Universal Serial Bus (USB) connector (which can include any of a number of different hardware interfaces), DisplayPort including MiniDisplayPort (MDP), High Definition Multimedia Interface (HDMI), Firewire, or other types.

[00111] Reference in the specification to "an embodiment," "one embodiment," "some embodiments," or "other embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments. The various appearances of "an embodiment," "one embodiment," or "some embodiments" are not necessarily all referring to the same embodiments. If the specification states a component, feature, structure, or characteristic "may," "might," or "could" be included, that particular component, feature, structure, or characteristic is not required to be included. If the specification or claim refers to "a" or "an" element, that does not mean there is only one of the elements. If the specification or claims refer to "an additional" element, that does not preclude there being more than one of the additional element.

[00112] Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment anywhere the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

[00113] While the disclosure has been described in conjunction with specific embodiments thereof, many alternatives, modifications and variations of such embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. The embodiments of the disclosure are intended to embrace all such alternatives, modifications, and variations as to fall within the broad scope of the appended claims.

[00114] In addition, well known power/ground connections to integrated circuit (IC) chips and other components may or may not be shown within the presented figures, for simplicity of illustration and discussion, and so as not to obscure the disclosure. Further, arrangements may be shown in block diagram form in order to avoid obscuring the disclosure, and also in view of the fact that specifics with respect to implementation of such block diagram arrangements are highly dependent upon the platform within which the present disclosure is to be implemented (i.e., such specifics should be well within purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the disclosure, it should be apparent to one skilled in the art that the disclosure can be practiced without, or with variation of, these specific details. The description is thus to be regarded as illustrative instead of limiting.

[00115] The following examples pertain to further embodiments. Specifics in the examples may be used anywhere in one or more embodiments. All optional features of the apparatus described herein may also be implemented with respect to a method or process.

[00116] Example 1 is an apparatus which comprises: a magnet; a stack of layers, a portion of which is adjacent to the magnet, wherein the stack of layers is to provide an inverse spin-orbit coupling effect; a layer exhibiting magnetoelectric properties; a conductor coupled to at least a portion of the stack of layers and the layer; and a capacitive device adjacent to the conductor such that the capacitive device is between the conductor and the layer exhibiting magnetoelectric properties.

[00117] Example 2 includes all features of example 1, wherein the magnet is a ferromagnet. [00118] Example 3 is according to any one of examples 1 to 2, wherein the magnet comprises one or a combination of materials which includes one or more of: a Heusler alloy, Co, Fe, Ni, Gd, B, Ge, Ga, permalloy, or Yttrium Iron Garnet (YIG), and wherein the Heusler alloy is a material which includes one or more of: Cu, Mn, Al, In, Sn, Ni, Sb, Ga, Co, Fe, Si, Pd, Sb, V, Ru, Cu ₂ MnAl, Cu ₂ MnIn, Cu ₂ MnSn, Ni ₂ MnAl, Ni ₂ MnIn, Ni ₂ MnSn, Ni ₂ MnSb, Ni ₂ MnGa Co ₂ MnAl, Co ₂ MnSi, Co ₂ MnGa, Co ₂ MnGe, Pd ₂ MnAl, Pd ₂ MnIn, Pd ₂ MnSn, Pd ₂ MnSb, Co ₂ FeSi, Co ₂ FeAl, Fe ₂ VAl, Mn ₂ VGa, Co ₂ FeGe, MnGa, MnGaRu, or Mn ₃ X, where 'X' is one of Ga or Ge.

[00119] Example 4 is according to any one of examples 1 to 3, wherein the stack of layers comprises: a first layer comprising Ag, wherein the first layer is adjacent to the magnet; and a second layer including one of: Bi or W, wherein the second layer is adjacent to the magnet and to the conductor.

[00120] Example 5 is according to any one of examples 1 to 3, wherein the conductor comprises a material which includes one or more of: Cu, Ag, Al, or Au.

[00121] Example 6 is according to any of the preceding examples, wherein capacitive device includes: a first layer comprising a conductive material; a dielectric; and a second layer comprising a conductive material, wherein the dielectric is between the first and second layers.

[00122] Example 7 is according to any one of examples 1 to 3, wherein the magnetoelectric layer with properties comprises a material which includes one of: Cr, O, CnCb or multiferroic material.

[00123] Example 8 includes all features of example 7, wherein the multiferroic material comprises BiFeC , LuFeC , LuFe204, or La doped BiFeC .

[00124] Example 9 includes all features of example 7, wherein the multiferroic material includes one of: Bi, Fe, O, Lu, or La.

[00125] Example 10 includes all features of example 1, wherein the stack of layers comprises a material which comprises one or more of: β-Ta, β-W, W, Pt, Cu doped with Iridium, Cu doped with Bismuth, or Cu doped an element of 3d, 4d, 5d, 4f, or 5f of periodic table groups.

[00126] Example 11 includes all features of example 1, and comprises a transistor coupled to the magnet.

[00127] Example 12 includes all features of example 1, wherein the magnet has in- plane magnetic anisotropy. [00128] Example 13 includes all features of example 1, wherein the magnet is a paramagnet.

[00129] Example 14 includes all features of example 13, wherein the magnet comprises a material which includes one or more of: Pt, Pd, W, Ce, Al, Li, Mg, Na, Cr ₂ 0 ₃ , CoO, Dy, Dy ₂ 0, Er, Er ₂ 0 ₃ , Eu, Eu ₂ 0 ₃ , Gd, Gd ₂ 0 ₃ , FeO, Fe ₂ 0 ₃ , Nd, Nd ₂ 0 ₃ , K0 ₂ , Pr, Sm, Sm ₂ 0 ₃ , Tb, Tb ₂ 0 ₃ , Tm, Tm ₂ 0 ₃ , V, or V ₂ 0 ₃ .

[00130] Example 15 is according to any of the preceding examples, wherein the capacitive device is to provide voltage amplification to voltage of the conductor.

[00131] Example 16 is an apparatus which comprises: a magnet having a first portion and a second portion; a stack of layers, a portion of which is adjacent to the first portion of the first magnet, wherein the first stack of layers is to provide an inverse spin orbit coupling effect; a magnetoelectric layer adjacent to the second portion; a conductor adjacent to the magnetoelectric layer; and a capacitive device adjacent to the conductor such that the capacitive device is between the conductor and the magnetoelectric layer.

[00132] Example 17 includes all features of example 16, and comprises: a second conductor adjacent to at least a portion of the stack of layers; a second magnet having a first portion and a second portion; a second magnetoelectric layer adjacent to the first portion of the second magnet; and a second stack of layers, a portion of which is adjacent to the second portion of the second magnet, wherein the second stack of layers is to provide an inverse spin orbit coupling effect; a third conductor adjacent to a portion of the second stack of layers; and a second capacitive device adjacent to the second conductor such that the second capacitive device is between the second conductor and the second magnetoelectric layer.

[00133] Example 18 includes all features of example 17, wherein the magnetoelectric layer and the second magnetoelectric layer include one or more of: Cr ₂ 0 ₃ or multiferroic material.

[00134] Example 19 includes all features of example 18, wherein magnetoelectric layer and the second magnetoelectric layer comprises a material which includes one of: Cr, O, Cr ₂ 0 ₃ or multiferroic material.

[00135] Example 20 includes all features of example 19, wherein the multiferroic material comprises BiFe0 ₃ , LuFeC , LuFe204, or La doped BiFe0 ₃ .

[00136] Example 21 includes all features of example 19, wherein the multiferroic material includes one of: Bi, Fe, O, Lu, or La.

[00137] Example 22 includes all features of example 19, wherein the stack of layers and the second stack of layers comprises a material which includes one or more of: β-Ta, β- W, W, Pt, Cu doped with Iridium, Cu doped with Bismuth, or Cu doped an element of 3d, 4d, 5d, 4f, or 5f of periodic table groups.

[00138] Example 23 according to any of examples 17 to 22, wherein the capacitive device and the second capacitive device include: a first layer comprising a conductive material; a dielectric; and a second layer comprising a conductive material, wherein the dielectric is between the first and second layers.

[00139] Example 24 according to any of examples 17 to 22, wherein the magnet and second magnet comprises a material which includes one or more of: Pt, Pd, W, Ce, Al, Li, Mg, Na, CnCb, CoO, Dy, Dy ₂ 0, Er, EnCb, Eu, EmCb, Gd, Gd2Cb, FeO, Fe203, Nd, Nd2Cb, KO2, Pr, Sm, Sm ₂ 0 ₃ , Tb, Tb ₂ 0 ₃ , Tm, Tm ₂ 0 ₃ , V, or V2O3.

[00140] Example 25 according to any of examples 17 to 22, wherein the magnet and second magnet comprises comprise one or a combination of materials which includes one or more of: a Heusler alloy, Co, Fe, Ni, Gd, B, Ge, Ga, permalloy, or Yttrium Iron Garnet (YIG), and wherein the Heusler alloy is a material which includes one or more of: Cu, Mn, Al, In, Sn, Ni, Sb, Ga, Co, Fe, Si, Pd, Sb, V, Ru, Cu ₂ MnAl, Cu ₂ MnIn, Cu ₂ MnSn, Ni ₂ MnAl, Ni ₂ MnIn, Ni ₂ MnSn, Ni ₂ MnSb, Ni ₂ MnGa Co ₂ MnAl, Co ₂ MnSi, Co ₂ MnGa, Co ₂ MnGe, Pd ₂ MnAl, PdJVInln, Pd ₂ MnSn, Pd ₂ MnSb, Co ₂ FeSi, Co ₂ FeAl, Fe ₂ VAl, Mn ₂ VGa, Co ₂ FeGe, MnGa, MnGaRu, or Mn ₃ X, where 'X' is one of Ga or Ge.

[00141] Example 26 is according to any of examples 16 to 25, wherein the capacitive device is to provide voltage amplification to voltage of the conductor.

[00142] Example 27 is a system which comprises: a memory; a processor coupled to the memory, the processor including an apparatus according to any one of apparatus examples 1 to 15 or apparatus examples 16 to 25; and a wireless interface to allow the processor to communicate with another device.

[00143] Example 28 is a method which comprises: forming a magnet; forming a stack of layers, a portion of which is adjacent to the magnet, wherein the stack of layers is to provide an inverse spin-orbit coupling effect; forming a layer exhibiting magnetoelectric properties; forming a conductor coupled to at least a portion of the stack of layers and the layer; and forming a capacitive device adjacent to the conductor such that the capacitive device is between the conductor and the layer exhibiting magnetoelectric properties.

[00144] Example 29 includes all features of example 28, wherein the magnet is a ferromagnet.

[00145] Example 30 is according to any one of examples 28 to 29, wherein the magnet comprises one or a combination of materials which includes one or more of: a Heusler alloy, Co, Fe, Ni, Gd, B, Ge, Ga, permalloy, or Yttrium Iron Garnet (YIG), and wherein the Heusler alloy is a material which includes one or more of: Cu, Mn, Al, In, Sn, Ni, Sb, Ga, Co, Fe, Si, Pd, Sb, V, Ru, Cu ₂ MnAl, Cu ₂ MnIn, Cu ₂ MnSn, Ni ₂ MnAl, Ni ₂ MnIn, Ni ₂ MnSn, Ni ₂ MnSb, Ni ₂ MnGa Co ₂ MnAl, Co ₂ MnSi, Co ₂ MnGa, Co ₂ MnGe, Pd ₂ MnAl, Pd ₂ MnIn, Pd ₂ MnSn, Pd ₂ MnSb, Co ₂ FeSi, Co ₂ FeAl, Fe ₂ VAl, Mn ₂ VGa, Co ₂ FeGe, MnGa, MnGaRu, or Mn ₃ X, where 'X' is one of Ga or Ge.

[00146] Example 31 is according to any one of examples 28 to 30, wherein forming the stack of layers comprises: forming a first layer comprising Ag, wherein the first layer is adjacent to the magnet; and forming a second layer including one of: Bi or W, wherein the second layer is adjacent to the magnet and to the conductor.

[00147] Example 32 is according to any one of examples 28 to 30, wherein the conductor comprises a material which includes one or more of: Cu, Ag, Al, or Au.

[00148] Example 33 is according to any of the preceding examples 28 to 32, wherein forming the capacitive device includes: forming a first layer comprising a conductive material; forming a dielectric; and forming a second layer comprising a conductive material, wherein the dielectric is between the first and second layers.

[00149] Example 34 is according to any one of examples 28 to 31, wherein the magnetoelectric layer with properties comprises a material which includes one of: Cr, O, CnCb or multiferroic material.

[00150] Example 35 includes all features of example 34, wherein the multiferroic material comprises BiFeC , LuFeC , LuFe204, or La doped BiFeC .

[00151] Example 36 includes all features of example 34, wherein the multiferroic material includes one of: Bi, Fe, O, Lu, or La.

[00152] Example 37 includes all features of example 28, wherein the stack of layers comprises a material which comprises one or more of: β-Ta, β-W, W, Pt, Cu doped with Iridium, Cu doped with Bismuth, or Cu doped an element of 3d, 4d, 5d, 4f, or 5f of periodic table groups.

[00153] Example 38 includes all features of example 28, and comprises forming a transistor coupled to the magnet.

[00154] Example 39 includes all features of example 28, wherein the magnet has in- plane magnetic anisotropy.

[00155] Example 40 includes all features of example 28, wherein the magnet is a paramagnet. [00156] Example 41 includes all features of example 40, wherein the magnet comprises a material which includes one or more of: Pt, Pd, W, Ce, Al, Li, Mg, Na, CnCb, CoO, Dy, Dy ₂ 0, Er, Er ₂ 0 ₃ , Eu, Eu ₂ 0 ₃ , Gd, Gd ₂ 0 ₃ , FeO, Fe ₂ 0 ₃ , Nd, Nd ₂ 0 ₃ , K0 ₂ , Pr, Sm, Sm ₂ 0 ₃ , Tb, Tb ₂ 0 ₃ , Tm, Tm ₂ 0 ₃ , V, or V ₂ 0 ₃ .

[00157] Example 42 is according to any of the preceding examples 28 to 41, wherein the capacitive device is to provide voltage amplification to voltage of the conductor.

[00158] Example 43 is a method which comprises: forming a magnet having a first portion and a second portion; forming a stack of layers, a portion of which is adjacent to the first portion of the first magnet, wherein the first stack of layers is to provide an inverse spin orbit coupling effect; forming a magnetoelectric layer adjacent to the second portion; forming a conductor adjacent to the magnetoelectric layer; and forming a capacitive device adjacent to the conductor such that the capacitive device is between the conductor and the

magnetoelectric layer.

[00159] Example 44 includes all features of example 43, and comprises: forming a second conductor adjacent to at least a portion of the stack of layers; forming a second magnet having a first portion and a second portion; forming a second magnetoelectric layer adjacent to the first portion of the second magnet; and forming a second stack of layers, a portion of which is adjacent to the second portion of the second magnet, wherein the second stack of layers is to provide an inverse spin orbit coupling effect; forming a third conductor adjacent to a portion of the second stack of layers; and forming a second capacitive device adjacent to the second conductor such that the second capacitive device is between the second conductor and the second magnetoelectric layer.

[00160] Example 45 includes all features of example 44, wherein the magnetoelectric layer and the second magnetoelectric layer include one or more of: Cr ₂ 0 ₃ or multiferroic material.

[00161] Example 46 includes all features of example 44, wherein magnetoelectric layer and the second magnetoelectric layer comprises a material which includes one of: Cr, O, Cr ₂ 0 ₃ or multiferroic material.

[00162] Example 47 includes all features of examples 46 or 45, wherein the multiferroic material comprises BiFe0 ₃ , LuFeC , LuFe204, or La doped BiFe0 ₃ .

[00163] Example 48 includes all features of examples 46 or 45, wherein the multiferroic material includes one of: Bi, Fe, O, Lu, or La.

[00164] Example 49 includes all features of example 48, wherein the stack of layers and the second stack of layers comprises a material which includes one or more of: β-Ta, β- W, W, Pt, Cu doped with Iridium, Cu doped with Bismuth, or Cu doped an element of 3d, 4d, 5d, 4f, or 5f of periodic table groups.

[00165] Example 50 is according to any of examples 44 to 49, wherein forming the capacitive device and the second capacitive device include: forming a first layer comprising a conductive material; forming a dielectric; and forming a second layer comprising a conductive material, wherein the dielectric is between the first and second layers.

[00166] Example 51 is according to any of examples 44 to 49, wherein the magnet and second magnet comprises a material which includes one or more of: Pt, Pd, W, Ce, Al, Li, Mg, Na, CnCb, CoO, Dy, Dy ₂ 0, Er, EnCb, Eu, EmCb, Gd, Gd2Cb, FeO, Fe203, Nd, Nd2Cb, KO2, Pr, Sm, Sm ₂ 0 ₃ , Tb, Tb ₂ 0 ₃ , Tm, Tm ₂ 0 ₃ , V, or V2O3.

[00167] Example 52 is according to any of examples 44 to 49, wherein the magnet and second magnet comprises comprise one or a combination of materials which includes one or more of: a Heusler alloy, Co, Fe, Ni, Gd, B, Ge, Ga, permalloy, or Yttrium Iron Garnet (YIG), and wherein the Heusler alloy is a material which includes one or more of: Cu, Mn, Al, In, Sn, Ni, Sb, Ga, Co, Fe, Si, Pd, Sb, V, Ru, Cu ₂ MnAl, Cu ₂ MnIn, Cu ₂ MnSn, Ni ₂ MnAl, Ni ₂ MnIn, Ni ₂ MnSn, Ni ₂ MnSb, Ni ₂ MnGa Co ₂ MnAl, Co ₂ MnSi, Co ₂ MnGa, Co ₂ MnGe, Pd ₂ MnAl, PdJVInln, Pd ₂ MnSn, Pd ₂ MnSb, Co ₂ FeSi, Co ₂ FeAl, Fe ₂ VAl, Mn ₂ VGa, Co ₂ FeGe, MnGa, MnGaRu, or Mn ₃ X, where 'X' is one of Ga or Ge.

[00168] Example 53 is according to any of examples 43 to 52, wherein the capacitive device is to provide voltage amplification to voltage of the conductor.

[00169] An abstract is provided that will allow the reader to ascertain the nature and gist of the technical disclosure. The abstract is submitted with the understanding that it will not be used to limit the scope or meaning of the claims. The following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.