INSULATING MAGNET

BACKGROUND

[0001] Spintronics is the study of intrinsic spin of the electron and its associated magnetic moment in solid-state devices. Spintronic logic are integrated circuit devices that use a physical variable of magnetization or spin as a computation variable. Such variables can be non-volatile (e.g., preserving a computation state when the power to an integrated circuit is switched off). Non-volatile logic can improve the power and computational efficiency by allowing architects to put a processor to un-powered sleep states more often and therefore reduce energy consumption. Existing spintronic logic generally suffer from high energy and relatively long switching times.

[0002] For example, large write current (e.g., greater than 100 mA/bit) and voltage

(e.g., greater than 0.7 V) are needed to switch a magnet (i.e., to write data to the magnet) in Magnetic Tunnel Junctions (MTJs). Existing Magnetic Random Access Memory (MRAM) based on MTJs also suffer from high write error rates (WERs) or low speed switching. For example, to achieve lower WERs, switching time is slowed down which degrades the performance of the MRAM. MTJ based MRAMs also suffer from reliability issues due to tunneling current in the spin filtering tunneling dielectric of the MTJs e.g., magnesium oxide (MgO).

BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The embodiments of the disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure, which, however, should not be taken to limit the disclosure to the specific embodiments, but are for explanation and understanding only.

[0004] Fig. 1A illustrates magnetization response to applied magnetic field for a ferromagnet.

[0005] Fig. IB illustrates magnetization response to applied magnetic field for a paramagnet.

[0006] Fig. 1C illustrates magnetization response to applied voltage field for a paramagnet connected to a magnetoelectric layer.

[0007] Fig. 2A illustrates a magnetoelectric spin orbit (MESO) logic using semi- insulating and/or insulating magnets, according to some embodiments of the disclosure. [0008] Fig. 2B illustrates a spin orbit material stack at the input of an interconnect, according to some embodiments of the disclosure.

[0009] Fig. 2C illustrates a magnetoelectric material stack at the output of an interconnect, according to some embodiments of the disclosure.

[0010] Fig. 3A illustrates a MESO logic operable as a repeater, according to some embodiments.

[0011] Fig. 3B illustrates a MESO logic operable as an inverter, according to some embodiments.

[0012] Fig. 4A illustrates a MESO logic using semi-insulating and/or insulating magnets, according to some embodiments of the disclosure.

[0013] Fig. 4B illustrates a spin orbit material stack at the input of an interconnect, according to some embodiments of the disclosure.

[0014] Fig. 4C illustrates a magnetoelectric material stack at the output of an interconnect, according to some embodiments of the disclosure.

[0015] Fig. 5A illustrates a top view of a layout of the MESO logic of Fig. 2A, according to some embodiments.

[0016] Fig. 5B illustrates a top view of a layout of the MESO logic of Fig. 4, according to some embodiments.

[0017] Fig. 6 illustrates a majority gate using MESO logic devices of Fig. 2A, according to some embodiments.

[0018] Fig. 7 illustrates a flowchart of a method for forming a MESO logic device, according to some embodiments of the disclosure.

[0019] Fig. 8 illustrates a smart device or a computer system or a SoC (System-on-

Chip) with MESO logic, according to some embodiments.

DETAILED DESCRIPTION

[0020] The Magnetoelectric (ME) effect has the ability to manipulate the magnetization (and the associated spin of electrons in the material) by an applied electric field. Since an estimated energy dissipation per unit area per magnet switching event through the ME effect is an order of magnitude smaller than with spin-transfer torque (STT) effect, ME materials have the capability for next-generation memory and logic applications.

[0021] Various embodiments describe a Magnetoelectric Spin Orbit (MESO) Logic which is a combination of various physical phenomena for spin-to-charge and charge-to-spin conversion, where the MESO logic comprises a semi-insulating and/or insulating magnet which forms a semi-insulating and/or insulating spin injection layer. In some embodiments, spin-to-charge conversion is achieved via one or more layers with the inverse Rashba- Edelstein effect (or spin Hall effect) wherein a spin current injected from an input magnet produces a charge current, and wherein the input conducting (or conductive) magnet is coupled to a semi-insulating magnet and/or insulating magnet via a coupling structure (e.g., materials such as Ru, Os, Hs, Fe, and other transition metals from the platinum group of the periodic table. The coupling layer also provides the effect of synthetic anti-ferromagnet because it is sandwiched between two magnets. In various embodiments, the magnetization of the free conducting magnet is forced on the insulating/semi-insulating magnet or vice- versa by the coupling layer. The sign of the charge current is determined by the direction of the injected spin and thus of magnetization. In some embodiments, charge-to-spin conversion is achieved via magnetoelectric effect in which the charge current produces a voltage on a capacitor, comprising a layer with magnetoelectric effect, leading to switching magnetization of an output magnet. In some embodiments, magnetic response of a magnet is according to an applied exchange bias from the magnetoelectric effect.

[0022] There are many technical effects of various embodiments. For example, high speed operation of the logic (e.g., 100 picoseconds (ps)) is achieved via the use of magnetoelectric switching operating on semi-insulating and/or insulating nanomagnets. In some examples, switching energy is reduced (e.g., 1-10 attojoules (aJ)) because the current needs to be“on” for a shorter time (e.g., approximately 3 ps) in order to charge the capacitor. In some examples, in contrast to the spin current, charge current does not attenuate when it flows through an interconnect. In some embodiments, the insulating and/or semi-insulating magnet in the MESO device mitigates fatigue of the ferro-electrics. For example, the insulating and/or semi-insulating magnet reduces the magneto-electric switching asymmetry, and also reduces the high DC in the spin-to-charge conversion module. The insulating and/or semi-insulating magnet also reduces the fatigue of the oxide based ferroelectric in the charge- to-magnet conversion module. Other technical effects will be evident from various embodiments and figures.

[0023] In the following description, numerous details are discussed to provide a more thorough explanation of embodiments of the present disclosure. It will be apparent, however, to one skilled in the art, that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring embodiments of the present disclosure. [0024] Note that in the corresponding drawings of the embodiments, signals are represented with lines. Some lines may be thicker, to indicate more constituent signal paths, and/or have arrows at one or more ends, to indicate primary information flow direction. Such indications are not intended to be limiting. Rather, the lines are used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit or a logical unit. Any represented signal, as dictated by design needs or preferences, may actually comprise one or more signals that may travel in either direction and may be implemented with any suitable type of signal scheme.

[0025] Throughout the specification, and in the claims, the term "connected" means a direct connection, such as electrical, mechanical, or magnetic connection between the things that are connected, without any intermediary devices.

[0026] The term "coupled" means a direct or indirect connection, such as a direct electrical, mechanical, or magnetic connection between the things that are connected or an indirect connection, through one or more passive or active intermediary devices.

[0027] The term“free” or“unfixed” here with reference to a magnet refers to a magnet whose magnetization direction can change along its easy axis upon application of an external field or force (e.g., Oersted field, spin torque, etc.). Conversely, the term“fixed” or “pinned” here with reference to a magnet refers to a magnet whose magnetization direction is pinned or fixed along an axis and which may not change due to application of an external field (e.g., electrical field, Oersted field, spin torque,).

[0028] Here, perpendicularly magnetized magnet (or perpendicular magnet, or magnet with perpendicular magnetic anisotropy (PMA)) refers to a magnet having a magnetization which is substantially perpendicular to a plane of the magnet or a device. For example, a magnet with a magnetization which is in a z-direction in a range of 90 (or 270) degrees +/- 20 degrees relative to an x-y plane of a device.

[0029] Here, an in-plane magnet refers to a magnet that has magnetization in a direction substantially along the plane of the magnet. For example, a magnet with a magnetization which is in an x or y direction and is in a range of 0 (or 180 degrees) +/- 20 degrees relative to an x-y plane of a device.

[0030] The term“device” may generally refer to an apparatus according to the context of the usage of that term. For example, a device may refer to a stack of layers or structures, a single structure or layer, a connection of various structures having active and/or passive elements, etc. Generally a device is a three dimensional structure with a plane along the x-y direction and a height along the z direction of an x-y-z Cartesian coordinate system. The plane of the device may also be the plane of an apparatus which comprises the device.

[0031] The term“adjacent” here generally refers to a position of a thing being next to

(e.g., immediately next to or close to with one or more things between them) or adjoining another thing (e.g., abutting it).

[0032] The term "circuit" or“module” may refer to one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function.

[0033] The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data/clock signal. The meaning of "a," "an," and "the" include plural references. The meaning of "in" includes "in" and "on."

[0034] The term“scaling” generally refers to converting a design (schematic and layout) from one process technology to another process technology and subsequently being reduced in layout area. The term“scaling” generally also refers to downsizing layout and devices within the same technology node. The term“scaling” may also refer to adjusting (e.g., slowing down or speeding up - i.e. scaling down, or scaling up respectively) of a signal frequency relative to another parameter, for example, power supply level. The terms “substantially,”“close,”“approximately,”“near, ” and“about,” generally refer to being within +/- 10% of a target value.

[0035] Unless otherwise specified the use of the ordinal adjectives“first,”“second,” and“third,” etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.

[0036] For the purposes of the present disclosure, phrases“A and/or B” and“A or B” mean (A), (B), or (A and B). For the purposes of the present disclosure, the phrase“A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0037] The terms“left,”“right,”“front,”“back,”“top,� �“bottom,”“over,”“under,” and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions.

[0038] For the purposes of present disclosure, the terms“spin” and“magnetic moment” are used equivalently. More rigorously, the direction of the spin is opposite to that of the magnetic moment, and the charge of the particle is negative (such as in the case of electron). [0039] It is pointed out that those elements of the figures having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0040] For purposes of the embodiments, the transistors in various circuits and logic blocks described here are metal oxide semiconductor (MOS) transistors or their derivatives, where the MOS transistors include drain, source, gate, and bulk terminals. The transistors and/or the MOS transistor derivatives also include Tri-Gate and FinFET transistors, Gate All Around Cylindrical Transistors, Tunneling FET (TFET), Square Wire, or Rectangular Ribbon Transistors, ferroelectric FET (FeFETs), or other devices implementing transistor functionality like carbon nanotubes or spintronic devices. MOSFET symmetrical source and drain terminals i.e., are identical terminals and are interchangeably used here. A TFET device, on the other hand, has asymmetric Source and Drain terminals. Those skilled in the art will appreciate that other transistors, for example, Bi-polar junction transistors— BJT PNP/NPN, BiCMOS, CMOS, eFET, etc., may be used without departing from the scope of the disclosure. The term“MN” indicates an n-type transistor (e.g., NMOS, NPN BJT, etc.) and the term“MP” indicates a p-type transistor (e.g., PMOS, PNP BJT, etc.).

[0041] Fig. 1A illustrates a magnetization hysteresis plot 100 for ferromagnet (FM)

101. The plot shows magnetization response to an applied magnetic field for ferromagnet 101. The x-axis of plot 100 is magnetic field Ή’ while the y-axis is magnetization‘m’. For FM 101, the relationship between Ή’ and‘m’ is not linear and results in a hysteresis loop as shown by curves 102 and 103. The maximum and minimum magnetic field regions of the hysteresis loop correspond to saturated magnetization configurations 104 and 106, respectively. In saturated magnetization configurations 104 and 106, FM 101 has stable magnetizations. In the zero magnetic field region 105 of the hysteresis loop, FM 101 does not have a definite value of magnetization, but rather depends on the history of applied magnetic fields. For example, the magnetization of FM 101 in configuration 105 can be either in the +X direction or the -x direction for an in-plane FM. As such, changing or switching the state of FM 101 from one magnetization direction (e.g., configuration 104) to another magnetization direction (e.g., configuration 106) is time consuming resulting in slower nanomagnets response time. It is associated with the intrinsic energy of switching proportional to the area in the graph contained between curves 102 and 103.

[0042] Fig. IB illustrates magnetization plot 120 for paramagnet 121. Plot 120 shows the magnetization response to an applied magnetic field for paramagnet 121. The x-axis of plot 120 is magnetic field Ή’ while the y-axis is magnetization‘m’. A paramagnet, as opposed to a ferromagnet, exhibits magnetization when a magnetic field is applied to it. Paramagnets generally have magnetic permeability greater or equal to one and hence are attracted to magnetic fields. Compared to plot 100, the magnetic plot 120 of Fig. IB does not exhibit hysteresis which allows for faster switching speeds and smaller switching energies between the two saturated magnetization configurations 124 and 126 of curve 122. In the middle region 125, paramagnet 121 does not have any magnetization because there is no applied magnetic field (e.g., H=0). The intrinsic energy associated with switching is absent in this case.

[0043] Fig. 1C illustrates plot 130 showing magnetization response to applied voltage field for a paramagnet 131 connected to a magnetoelectric layer 132. Here, the x-axis is voltage‘V’ applied across ME layer 132 and y-axis is magnetization‘m’. Ferroelectric polarization“PEE” in ME layer 132 is indicated by an arrow. In this example, magnetization is driven by exchange bias exerted by a ME effect from ME layer 132. When positive voltage is applied to ME layer 132, paramagnet 131 establishes a deterministic magnetization (e.g., in the +x direction by voltage +V _C ) as shown by configuration 136. When negative voltage is applied by ME layer 132, paramagnet 131 establishes a deterministic

magnetization (e.g., in the -x direction by voltage -V _c ) as shown by configuration 134. Plot 130 shows that magnetization functions l33a and l33b have hysteresis. In some

embodiments, by combining ME layer 132 with paramagnet 131, switching speeds of paramagnet as shown in Fig. IB are achieved. In some embodiments, the hysteresis behavior of FM 131, as shown in Fig. 1C, is associated with the driving force of switching rather than the intrinsic resistance of the magnet to switching.

[0044] Fig. 2A illustrates a magnetoelectric spin orbit (MESO) logic 200 using semi- insulating or insulating magnet, according to some embodiments of the disclosure. Fig. 2B illustrates a material stack at the input of an interconnect, according to some embodiments of the disclosure. Fig. 2C illustrates a magnetoelectric material stack at the output of an interconnect, according to some embodiments of the disclosure.

[0045] In some embodiments, MESO logic 200 comprises a first magnet 201, a spin orbit coupling (SOC) structure having a stack of layers (e.g., layers 202, 203, and 204, also labeled as 202a/b, 203a/b, and 204a/b), interconnecting conductor 205 (e.g., a non-magnetic charge conductor), magnetoelectric (ME) structure 206 (206a/b), second magnet 207, first insulating or semi-insulating magnet 2l2b, second insulating or semi-insulating magnet 2l2a, first coupling structure 2l3b, second coupling structure 2l3a, metal contacts 209a/b, and transistors MN1, MP1, MN2, and MP2. The first and second magnets 201 and 207 are also referred to as first and second conducting free magnets, respectively.

[0046] In some embodiments, the first and second conducting magnets 201 and 207, respectively, have in-plane magnetic anisotropy. For example, first and second conducting magnets 201 and 207 have a magnetization pointing along the -y/+y direction and is along the x-y plane of the device 200. In some embodiments, first magnet 201 comprises first and second portions, wherein the first portion of first magnet 201 is adjacent to the first insulating or semi-insulating magnet 2l2b via first coupling structure 2l3b. As such, a synthetic anti- ferromagnet is formed, and magnetization of one magnet can be induced on the other magnet but with opposite direction.

[0047] In some embodiments, the insulating (insulative) or semi-insulating (semi- insulative) magnet 212b is adjacent to ME structure 206b, which in turn is adjacent to input conductor 21 la that provides input charge current I _C har _g e(iN). In some embodiments, the second portion of first magnet 201 is adjacent to a SOC structure (e.g., structure comprising layers 202a, 203a, 204a in a stack). In various embodiments, conductor 205 is adjacent to a portion of the SOC structure. For example, conductor 205 is adjacent to layer 204a and/or layer 203a.

[0048] In some embodiments, second conducting magnet 207 comprises first and second portions, wherein the first portion of second conducting magnet 207 is adjacent to the second insulating or semi-insulating magnet 2l2a via second coupling structure 2l3a. As such, another synthetic anti-ferromagnet is formed, and magnetization of one magnet can be induced on the other magnet but with opposite direction. In various embodiments, the first and second coupling structures 2l3b/a provide exchange interaction which ensures that magnetization of one magnet is opposite a magnetization of the other magnet. In various embodiments, the first and second coupling structures 2l3b/a have a thickness in a range of 0.70 nm to 95 nm. For example, the first and second coupling structures 2l3b/a comprise Ru with a thickness of 0.85 nm.

[0049] In some embodiments, the insulating or semi-insulating magnet 2l2a is adjacent to ME structure 206a, which in turn is adjacent to conductor 205. In some embodiments, the second portion of second conducting magnet 207 is adjacent to another SOC structure (e.g., structure comprising layers 202b, 203b, 204b in a stack). In various embodiments, the other SOC structure is adjacent to an output conductor 21 lb which is to provide an output charge current I _C har _g e(ouT). In some embodiments, conductor 205 (or charge interconnect) is coupled to at least a portion of the stack of layers (e.g., one of layers 202a, 203a, or 204a) and ME layer 206a. For example, conductor 205 is coupled to layer 204a of the stack.

[0050] In some embodiments, the SOC structure or stack of layers (e.g., layers

202a/b, 203a/b, or 204a/b) is to provide an inverse Rashba-Edelstein effect (or inverse spin Hall effect). In some embodiments, the SOC or the stack of layers provide spin-to-charge conversion where a spin current 7 _S (or spin energy J _s ) is injected from first conducting magnet 201 and charge current I _c is generated by the stack of layers. This charge current I _c is provided to conductor 205 (e.g., charge interconnect). In contrast to spin current, charge current does not attenuate in conductor 205. The direction of the charge current I _c depends on the direction of magnetization of first conducting magnet 201. The direction of the charge current I _c also depends on the direction of magnetization of first semi-insulating magnet 2l2b.

[0051] In some embodiments, first insulating or semi-insulating magnet 2l2b functions as a displacement capacitor between transistor MN1 and first magnet 201. Here the term“semi-insulating magnet” or“insulating magnet” generally refers to a material that has magnetic properties but has higher resistivity compared to normal ferromagnets. For example, semi-insulating or insulating magnets may not be conductive for charge current, but may exhibit magnetic properties. The semi-insulating magnet or insulating magnet may have a Spinel crystal structure, can be hexagonal (e.g., Fe ₂ 0 ₃ ), or they can belong to any of the crystal classes. In some embodiments, materials for semi-insulating or insulating magnets include one of: Fe ₂ 0 ₃ , C02O3, Co ₂ Fe0 ₄ , or Ni ₂ Fe0 ₄ . In some embodiments, elements for semi-insulating or insulating magnets include one or more of: Fe _, O _, Co or Ni.

[0052] In some embodiments, first insulating/semi-insulating magnet 2l2b and second insulating/semi-insulating magnet 2l2a form displacement capacitors. The nature of the displacement capacitor may be set by the leakage and the dielectric constants of the semi- insulating magnets 2l2a/b. In some embodiments, first insulating/semi-insulating magnet 2l2b and second insulating/semi-insulating magnet 2l2a form dielectric capacitors, where a bound charge is generated at the plates.

[0053] In some embodiments, the charge current I _c charges the capacitor around ME structure 206a and switches its polarization. ME structure 206a exerts exchange bias on second magnet layer 207 via insulating/semi-insulating magnet 2l2a, and the direction of the exchange bias determines the magnetization of second conducting magnet 207. The same dynamics occurs by ME layer 206b which exerts exchange bias on first conducting magnet 201 via insulating/semi-insulating magnet 212a according to input charge current on conductor 21 la.

[0054] In some embodiments, the magnetization of first insulating or semi-insulating magnet 2l2b is determined by the magnetization of first magnet 201. For example, when first magnet 201 has magnetizations pointing in -y direction, then first insulating or semi- insulating magnet 212b has magnetization pointing in the -i-y direction. In some

embodiments, the magnetization of second semi-insulating magnet 2l2a is determined by the magnetization of second magnet 207. For example, when second magnet 207 has magnetizations pointing in -y direction, then second insulating or semi-insulating magnet 212a has magnetization pointing in the -i-y direction.

[0055] In this example, the length of first magnet 201 is L _m , the width of conductor

205 is W _c , the length of conductor 205 from the interface of layer 204a to ME structure 206a is L _c , t _c is the thickness of the conducting magnets 201 and 207, and t _ME is the thickness of ME structure 206a. In some embodiments, conductor 205 comprises a material including one of: Cu, Ag, Al, Au, graphene, etc.

[0056] In some embodiments, the input and output charge conductors (21 la and

21 lb, respectively) and associated spin-to-charge and charge-to-spin converters are provided. In some embodiments, input charge current I _C har _g e(iN) is provided on interconnect 21 la (e.g., charge interconnect made of same material as interconnect 205). In some embodiments, interconnect 21 la is coupled to first magnet 201 via ME layer 206b, insulating/semi- insulating magnet 2l2b and coupling structure 2l3b. In some embodiments, interconnect 21 la is orthogonal to first magnet 201. For example, interconnect 21 la extends in the +X direction while first magnet 201 extends in the -y direction. In some embodiments, I _C har _g e(iN) is converted to corresponding magnetic polarization of 201 by ME structure 206b. The materials for ME layers 206a/b are the same as the materials of ME structure 206.

[0057] In some embodiments, an output interconnect 21 lb is provided to transfer output charge current I _C har _g e(ouT) to another logic or stage. In some embodiments, the output interconnect 21 lb is coupled to second conducting magnet 207 via an SOC structure (e.g., stack of layers) that exhibits spin Hall effect and/or Rashba Edelstein effect. For example, layers 202b, 203b, and 204b are provided as a stack to couple output interconnect 21 lb with second conducting magnet 207. Material wise, layers 202b, 203b, and 204b are formed of the same material as layers 202a, 203a, and 204a, respectively. In some embodiments, second insulating/semi-insulating magnet 212a is adjacent to second conducting magnet 207 via coupling structure 2l3a. [0058] In some embodiments, a transistor (e.g., p-type transistor MP1) is coupled to first conducting magnet 201 via contact 209a (e.g., Cu, Al, Ag, or Au, etc.). In this example, the source terminal of MP1 is coupled to a supply V _dd , the gate terminal of MP1 is coupled to a control voltage V _ci (e.g., a switching clock signal, which switches between V _dd and ground), and the drain terminal of MP1 is coupled to first magnet 201 via contact 209a. In some embodiments, contact 209a is made of any suitable conducting material used to connect the transistor to the first magnet 201. In some embodiments, the current I _drive from transistor MP1 generates spin current into the stack of layers (e.g., layers 202a, 203a, and 204a).

[0059] In some embodiments, along with the p-type transistor MP1 connected to V _dd

(or an n-type transistor connected to V _dd but with gate overdrive above V _dd ), an n-type transistor MN1 is provided which couples to first magnet 201 via contact 209a, where the n- type transistor is operable to couple ground (or 0 V) to first magnet 201. In some

embodiments, n-type transistor MN2 is provided which is operable to couple ground (or 0V) to second magnet 207 via contact 209b.

[0060] In some embodiments, p-type transistor MP2 is provided which is operable to couple power supply (V _dd or -V _dd ) to second conducting magnet 207 via contact 209b. For example, when clock is low (e.g., V _ci =0 V), then transistor MP1 is on and V _dd is coupled to first conducting magnet 201 (e.g., power supply is V _dd ) and 0V is coupled to second conducting magnet 207. This provides a potential difference for charge current to flow. Continuing with this example, when clock is high (e.g., V _ci =V _dd and power supply is V _dd ), then transistor MP1 is off, transistor MN1 is on, and transistor MN2 is off. As such, 0 V is coupled to first conducting magnet 201.

[0061] In some embodiments, the power supply is a negative power supply (e.g., -

V _dd ). In that case, then transistor MPl’s source is connected to 0 V, and transistor MNl’s source is connected to -V _dd , and transistor MN2 is on. When V _ci = 0 V and power supply is - V _dd , then transistor MN1 is on, and transistor MP1 is off, and transistor MN2 (whose source is at -V _dd ) is off and MP2 whose source is 0 V is on. In this case, -V _dd is coupled to input magnet 201 and 0 V is coupled to output magnet 207 via respective contacts 209a/b. This also provides a path for charge current to flow. Continuing with this example, when the clock is high (e.g., V _ci =-V _dd and power supply is -V _dd ), then transistor MP1 is off, transistor MN1 is on, and transistor MN2 is off. As such, 0 V is coupled to input magnet 201.

[0062] In some embodiments, ME structure 206a/b forms the magnetoelectric capacitor to switch the conducting magnets 201/207. For example, the conductor 205 forms one plate of the capacitor, insulating/semi-insulating magnet 2l3a forms the other plate of the capacitor, and ME structure 206a is the magnetic-electric oxide that provides out-of-plane exchange bias to second magnet 207 via insulating/semi-insulating magnet 2l3a. In some embodiments, the magnetoelectric oxide comprises perpendicular exchange bias due to partially compensated anti-ferromagnetism.

[0063] In some embodiments, first magnet 201 injects a spin polarized current into the high spin-orbit coupling (SOC) material stack (e.g., layers 202a, 203a, and 204a). The spin polarization is determined by the magnetization of first magnet 201 (which is same as magnetization of first semi-insulating magnet 2l2b).

[0064] In some embodiments, the stack comprises i) an interface 203a/b with a high density 2D (two dimensional) electron gas and with high SOC formed between 202a/b and 204a/b materials such as i) Ag or Bi, or ii) a bulk material 204 with high Spin Hall Effect (SHE) coefficient such as Ta, W, or Pt. In some embodiments, a spacer (or template layer) is formed between first magnet 201 and the injection stack. In some embodiments, this spacer is a templating metal layer which provides a template for forming first magnet 201. In some embodiments, the metal of the spacer which is directly coupled to first magnet 201 is a noble metal (e.g., Ag, Cu, or Au) doped with other elements from Group 4d and/or 5d of the Periodic Table. In some embodiments, first magnet 201 (and by extension first semi- insulating magnet 209a) are sufficiently lattice matched to Ag (e.g., a material which is engineered to have a lattice constant close (e.g., within 3%) to that of Ag).

[0065] In some embodiments, the 2D materials include one or more of: Mo, S, W, Se,

Graphene, M0S2, WSe ₂ , WS2, or MoSe2. In some embodiments, the 2D materials include an absorbent which includes one or more of: Cu, Ag, Pt, Bi, Fr, or H absorbents. In some embodiments, the SOC structures comprise a spin orbit material which includes materials that exhibit Rashba-Bychkov effect. In some embodiments, material which includes materials that exhibit Rashba-Bychkov effect comprises materials ROCI12, where‘R’ includes one or more of: La, Ce, Pr, Nd, Sr, Sc, Ga, Al, or In, and where“Ch” is a chalcogenide which includes one or more of: S, Se, or Te.

[0066] Here, sufficiently matched atomistic crystalline layers refer to matching of the lattice constant‘a’ within a threshold level above which atoms exhibit dislocation which is harmful to the device (for instance, the number and character of dislocations lead to a significant (e.g., greater than 10%) probability of spin flip while an electron traverses the interface layer). For example, the threshold level is within 5% (i.e., threshold levels in the range of 0% to 5% of the relative difference of the lattice constants). As the matching improves (e.g., matching gets closer to perfect matching), spin injection efficiency from spin transfer from first conducting magnet 201 to first ISHE/ISOC stacked layer increases. Poor matching (e.g., matching worse than 5%) implies dislocation of atoms that is harmful for the device.

[0067] Table 1 summarizes transduction mechanisms for converting magnetization to charge current and charge current to magnetization for bulk materials and interfaces.

Table 1: Transduction mechanisms for Spin to Charge and Charge to Spin Conversion

[0068] The following section describes the spin to charge and charge to spin dynamics. In some embodiments, the spin-orbit mechanism responsible for spin-to-charge conversion is described by the inverse Rashba-Edelstein effect in 2D electron gases. The Hamiltonian (energy) of spin-orbit coupling electrons in a 2D electron gas is:

H _R = a _R (k x z) . s

where a _R is the Rashba-Edelstein coefficient,‘k’ is the operator of momentum of electrons, z is a unit vector perpendicular to the 2D electron gas, and s is the operator of spin of electrons.

[0069] The spin polarized electrons with direction of polarization in-plane (e.g., in the xy-plane) experience an effective magnetic field dependent on the spin direction:

a _R .

B(k)=— ( k x z )

/½

where /r _B is the Bohr magneton.

[0070] This results in the generation of a charge current I _c in interconnect 205 proportional to the spin current 7 _S (or J _s ). The spin-orbit interaction by Ag and Bi interface layers 202 and 204 (e.g., the Inverse Rashba-Edelstein Effect (IREE)) produces a charge current I _c in the horizontal direction given as:

where w _m is width of the input conducting magnet 201, and l _IKEE is the IREE constant (with units of length) proportional to a _R .

[0071] Alternatively, the Inverse Spin Hall Effect in Ta, W, or Pt layer 203a/b produces the horizontal charge current I _c given as: [0072] Both IREE and ISHE effects produce spin-to-charge current conversion around 0.1 with existing materials at 10 nm (nanometers) magnet width. For scaled nanomagnets (e.g., 5 nm wide magnets) and exploratory SHE materials such as Bi ₂ Se3, the spin-to-charge conversion efficiency can be between 1 and 2.5. The net conversion of the drive charge current 1 _drive to magnetization dependent charge current is given as:

where‘P’ is the dimensionless spin polarization. For this estimate, the drive current idm _< · and the charge current I _c = I _d = 100 mA is set. As such, when estimating the resistance of the ISHE interface to be equal to R = 100 W, then the induced voltage is equal to V _ISHE =

10 mV.

[0073] The charge current I _c , carried by interconnect 205, produces a voltage on the capacitor of ME structure 206a comprising magnetoelectric material dielectric (such as BiFeCb (BFO) or O2O3) in contact with second insulating/semi-insulating magnet 2l2a (which serves as one of the plates of the capacitor) and interconnect 205 (which series as the other of the plates of the capacitor). In some embodiments, magnetoelectric materials are either intrinsic multiferroic or composite multiferroic structures. As the charge accumulates on the magnetoelectric capacitor of ME structure 206a, a strong magnetoelectric interaction causes the switching of magnetization in second insulating or semi-insulating magnet 212a (and by extension second conducting magnet 207).

[0074] For the following parameters of the magnetoelectric capacitor: thickness t _ME = 5 nm, dielectric constant e = 500, area A = 60 nm x 20 nm. Then the capacitance is given as:

ee _h A

C = « IfF

t-ME

[0075] Demonstrated values of the magnetoelectric coefficient is a _ME ~10/c , where the speed of light is c. This translates to the effective magnetic field exerted on second semi- insulating magnet 207, which is expressed as:

BME = a _ME E = ^aMEV,SHE -0.06 T

t ME

This is a strong field sufficient to switch magnetization.

[0076] The charge on the capacitor of ME layer 206a is Q =— x 10 mV = 10 aC,

fF

and the time to fully charge it to the induced voltage is td = 10— ~1 ps (with the account of

Id decreased voltage difference as the capacitor charges). If the driving voltage is V _d =

100 mV, then the energy E _sw to switch is expressed as:

E _sw ~100mV x IOOmA x lps~10aj

which is comparable to the switching energy of CMOS transistors. Note that the time to switch t _sw magnetization remains much longer than the charging time and is determined by the magnetization precession rate. The micro-magnetic simulations predict this time to be t _sw ~100ps, for example.

[0077] In some embodiments, materials for first and second magnets 201 and 207 have saturated magnetization M _s and effective anisotropy field H _k . Saturated magnetization M _s is generally the state reached when an increase in applied external magnetic field H cannot increase the magnetization of the material. Anisotropy H _k generally refers material properties that are highly directionally dependent.

[0078] In some embodiments, materials for first and second magnets 201 and 207, respectively, are non- ferromagnetic elements with strong paramagnetism which have high number of unpaired spins but are not room temperature ferromagnets. A paramagnet, as opposed to a ferromagnet, exhibits magnetization when a magnetic field is applied to it. Paramagnets generally have magnetic permeability greater or equal to one and hence are attracted to magnetic fields. In some embodiments, magnets 209a/b and 210a/b comprise a material which includes one or more of: Platinum(Pt), Palladium (Pd), Tungsten (W), Cerium (Ce), Aluminum (Al), Lithium (Li), Magnesium (Mg), Sodium (Na), CnCL (chromium oxide), CoO (cobalt oxide), Dysprosium (Dy), Dy ₂ 0 (dysprosium oxide), Erbium (Er), EnCL (Erbium oxide), Europium (Eu), E _¾( ¾ (Europium oxide), Gadolinium (Gd), Gadolinium oxide (Gd ₂ 03), FeO and Fe ₂ 03 (Iron oxide), Neodymium (Nd), Nd ₂ 03 (Neodymium oxide), K0 ₂ (potassium superoxide), praseodymium (Pr), Samarium (Sm), Sm ₂ 0 ₃ (samarium oxide), Terbium (Tb), Tb ₂ 0 ₃ (Terbium oxide), Thulium (Tm), Tm ₂ 0 ₃ (Thulium oxide), or V ₂ 0 ₃ (Vanadium oxide). In some embodiments, the first and second paramagnets 201 and 207 comprise dopants selected from a group which includes one or more of: Ce, Cr, Mn, Nb, Mo, Tc, Re, Nd, Gd, Tb, Dy, Ho, Er, Tm, or Yb.

[0079] In some embodiments, first and second magnets 201 and 207, respectively, are ferromagnets. In some embodiments, first and second magnets 201 and 207, respectively, comprise one or a combination of materials which includes one or more of: a Heusler alloy, Co, Fe, Ni, Gd, B, Ge, Ga, permalloy, or Yttrium Iron Garnet (YIG), and wherein the Heusler alloy is a material which includes one or more of: Cu, Mn, Al, In, Sn, Ni, Sb, Ga, Co, Fe, Si, Pd, Sb, V, Ru, Cu ₂ MnAl, Cu ₂ MnIn, Cu ₂ MnSn, Ni ₂ MnAl, Ni ₂ MnIn, Ni ₂ MnSn, Ni ₂ MnSb, Ni ₂ MnGa Co ₂ MnAl, Co ₂ MnSi, Co ₂ MnGa, Co ₂ MnGe, Pd ₂ MnAl, Pd ₂ MnIn, Pd ₂ MnSn, Pd ₂ MnSb, Co ₂ FeSi, Co ₂ FeAl, Fe ₂ VAl, Mn ₂ VGa, Co ₂ FeGe, MnGa, MnGaRu, or Mn ₃ X, where ‘X’ is one of Ga or Ge.

[0080] In some embodiments, first and second insulating or semi-insulating magnets

2l2b and 2l2a, respectively, comprise a material which includes one or more of: Co, Fe, No, or O. In some embodiments, the first and second insulating or semi-insulating magnets 2l2b and 2l2a, respectively, comprise a material which includes one or more of: C02O3, Fe203, Co2Fe0 ₄ , or NFFeO^ In some embodiments, first and second insulating or semi-insulating magnets 212b and 212a have Spinel crystal structure. In some embodiments, magnets 212b and 2l2a have conducting properties. For example, magnets 2l2b and 2l2a can be insulating paramagnets or ferromagnets.

[0081] In some embodiments, the SOC structures (e.g., stack of layers providing spin orbit coupling) comprises: a first layer 202a/b comprising Ag, wherein the first layer is adjacent to magnets 201/207; and a second layer 204a/b comprising Bi or W, wherein second layer 204a/b is adjacent to first layer 202a/b and to a conductor (e.g., 205, 21 lb). In some embodiments, a third layer 203a/b (having material which is one or more of Ta, W, or Pt) is sandwiched between first layer 202a/b and second layer 204a/b as shown. In some embodiments, the stack of layers comprises a material which includes one of: b-Ta, b-W, W, Pt, Cu doped with Iridium, Cu doped with Bismuth, or Cu doped an element of 3d, 4d, 5d, 4f, or 5f of periodic table groups.

[0082] In some embodiments, ME structure 206a/b comprises a material which includes one of: &2O3 and multiferroic material. In some embodiments, ME structure 206 comprises Cr and O. In some embodiments, the multiferroic material comprises BFO (e.g., BiFeOs), LFO (LuFe0 ₂ , LuFe ₂ 0 ₄ ), or La doped BiFe0 ₃ . In some embodiments, the multiferroic material includes one of: Bi, Fe, O, Lu, or La. In some embodiments, ME structure 206a/b comprises one of: dielectric, para-electric, or ferro-electric material.

[0083] Fig. 3A illustrates MESO logic 300 operable as a repeater (or buffer), according to some embodiments. In some embodiments, to configure MESO logic 200 (now shown as logic 300) as a repeater, a portion of the stack of the layers (e.g., layer 204a/b) is coupled to ground, first insulating semi-insulating magnet 212b is coupled to a negative supply (e.g., -V _dd ) via transistor MP1, and second insulating/semi-insulating magnet 2l2a is coupled to ground (e.g., 0V) via transistor MN2. In some embodiments, for repeater MESO logic 300, the magnetization direction of first magnet 201 (and by extension magnetization of first insulating/semi-insulating magnet 2l2b) is the same as the magnetization direction of second magnet 207 (and by extension magnetization of second insulating/semi-insulating magnet 2l2a). For example, the magnetization direction of first magnet 201 is in the -i-y direction while the magnetization direction of second magnet 207 is also in the -i-y direction.

[0084] Fig. 3B illustrates MESO logic 320 operable as an inverter, according to some embodiments. In some embodiments, to configure the MESO logic 200 (now shown as logic 320) as an inverter, a portion of the stack of the layers (e.g., layer 204a/b) is coupled to ground, first insulating/semi-insulating magnet 2l2b is coupled to a positive supply (e.g., +V _dd ) via transistor MP1, and second insulating/semi-insulating structure 2l2a is coupled to ground (e.g., 0 V). In some embodiments, for inverter SOL 320, the magnetization direction of first magnet 201 (and by extension first insulating/semi-insulating magnet 2l2b) is opposite compared to the magnetization direction of second magnet 207 (and by extension the second insulating/semi-insulating magnet 2l2a). For example, the magnetization direction of first magnet 201 is in the -i-y direction while the magnetization direction of second magnet 207 is in the -y direction.

[0085] MESO logic devices of various embodiments provide logic cascadability and unidirectional signal propagation (e.g., input-output isolation). The unidirectional nature of logic is ensured due to large difference in impedance for injection path versus detection path, in accordance with some embodiments. In some embodiments, the injector is essentially a metallic spin valve with spin to charge transduction with RA (resistance area) products of approximately 10 mOhm.micron ² . In some embodiments, the detection path is a low leakage capacitance with RA products much larger than 1 MOhm.micron ² in series with the resistance of the FM capacitor plate with estimated resistance greater than 500 Ohms.

[0086] Fig. 4A illustrates a MESO logic 400 using semi-insulating and/or insulating magnets, according to some embodiments of the disclosure. MESO logic 400 is essentially the same as MESO logic 200 but for the stacking of insulating/semi-insulating magnets 2l2b/a (now referred to as 4l2b/a, respectively) relative to the conducting magnets 201/207 (now referred to as 401/407, respectively). Fig. 4B illustrates a spin orbit material stack at the input of an interconnect, according to some embodiments of the disclosure. Fig. 4C illustrates a magnetoelectric material stack at the output of an interconnect, according to some embodiments of the disclosure.

[0087] Here, insulating magnets 4l2b/4l2a are formed on top of magnets 401/407, respectively, while coupling structures 4l3b/a couple the insulating magnets 4l2b/4l2a with the conducting magnets 401/407, respectively. In various embodiments, the transistors are coupled to the first and second conducting magnets 401/407 via contacts 409a/b, respectively. Material wise, insulating magnets 4l2b/4l2a are the same as insulating/semi-insulating magnets 2l2b/2l2a, respectively; materials for magnets 401/407 are same as materials for materials for magnets 201/207, respectively; materials for coupling structures 4l3a/4l3b are same as materials for materials for magnets 2l3a/2l2b, respectively, and materials for contacts 409a/b are same as materials for contacts 209a/b, respectively. Technical effect wise, MESO logic 400 behaves similarly as MESO logic 200. As such, inverter and repeater functions can be realized using MESO logic 400 in the same was as repeater and inverter functions are released MESO logic 200 as described with reference to Figs. 3A-B.

[0088] Fig. 5A illustrates a top view 500 of a layout of the MESO logic of Fig. 2A, according to some embodiments. An integration scheme for MESO devices with CMOS drivers for power supply and clocking is shown in the top view. Here, transistor MP1 is formed in the active region 501, and power supply is provided via metal layer 3 (M3) indicated as 506. The gate terminal 504 of transistor MP1 is coupled to a supply interconnect 505 through via or contact 503. In some embodiments, M3 layer 507 is coupled to ground which provides ground supply to layer 204. In some embodiments, another transistor can be formed in active region 503 with gate terminal 510. Here, 508 and 509 are contact vias coupled to power supply line. In some embodiments, the density of integration of the devices exceeds that of CMOS since an inverter operation can be achieved within 2.5P x 2M0. In some embodiments, since the power transistor MP1 can be shared among all the devices at the same clock phases, vertical integration can also be used to increase the logic density as described with reference to Fig. 6, in accordance with some embodiments. Fig. 5B illustrates a top view of a layout of the MESO logic of Fig. 4, according to some embodiments.

[0089] Fig. 6 illustrates a majority gate using MESO logic 600 devices of Fig. 2A, according to some embodiments. A charge mediated majority gate is proposed using the spin orbit coupling and magnetoelectric switching. A charge mediated majority gate is shown in Fig. 6. Majority gate 600 comprises at least three input stages 601, 602, and 603 with their respective charge conductors 205 ₁ , 205 ₂ , and 205 ₃ coupled to summing interconnect 604. In some embodiments, summing interconnect 604 is made of the same materials as interconnect 205. In some embodiments, summing interconnect 604 is coupled to output stage 605 which includes the second magnet 507 (like 207). The three input stages 601, 602, and 603 share a common power/clock region therefore the power/clock gating transistor can be shared among the three inputs of the majority gate, in accordance with some embodiments. The input stages 601, 602, and 603 can also be stacked vertically to improve the logic density, in accordance with some embodiments. The charge current at the output (I _Charge( ou _T) ) is the sum of currents I _Chi , Ich2, and I _Ch 3·

[0090] Fig. 7 illustrates a flowchart 700 of a method for forming a MESO logic device, according to some embodiments of the disclosure. While blocks or operations of flowchart 700 are shown in a particular order, the order can be changed. For example, some blocks or operations can be performed before others while some can be performed simultaneously.

[0091] At block 701, a first conducting magnet (e.g., magnet 201/401) is formed with non-insulating properties or conducting properties. In some embodiments, the method for forming the first magnet comprises forming one of a paramagnet or ferromagnet. In some embodiments, the method of forming the first magnet comprises forming a material which includes one or more of: Pt, Pd, W, Ce, Al, Li, Mg, Na, Cr, O, Co, Dy, Er, Eu, Gd, Fe, Nd, K, Pr, Sm, Tb, Tm, or V. In some embodiments, the method of forming the first conducting magnet 201/401 comprises forming one or a combination of materials which includes one or more of: a Heusler alloy, Co, Fe, Ni, Gd, B, Ge, Ga, permalloy, or Yttrium Iron Garnet (YIG), and wherein the Heusler alloy is a material which includes one or more of: Cu, Mn,

Al, In, Sn, Ni, Sb, Ga, Co, Fe, Si, Pd, Sb, Si, V, or Ru.

[0092] At block 702, a first SOC structure (e.g., coupling layer 2l3a/b such as Ru,

Hs, Os) is formed adjacent to the first magnet. In some embodiments, the method of forming the first structure comprises forming a material having one or more of: Ru, Os, Hs, Fe, or other transition metals from a platinum group of the periodic table.

[0093] At block 703, a second conducting magnet 207/407 is formed with semi- insulating or insulating properties, wherein the second magnet is adjacent to the first structure. In some embodiments, the method of forming the second magnet comprises forming a material which includes one or more of: Co, Fe, Ni, or O. In some embodiments, the first and second magnets have in-plane magnetic anisotropy.

[0094] At block 704, a second SOC structure is formed, a portion of which is adjacent to the first magnet with non-insulating properties, wherein the second structure is to provide an inverse spin-orbit coupling effect. In some embodiments, the method of forming the second structure comprises: forming a fourth structure comprising Ag, wherein the fourth structure is adjacent to the first magnet; and forming a fifth structure including one of: Bi or W, wherein the fifth structure is adjacent to the first magnet and to a conductor. In some embodiments, the method of forming the conductor comprises forming a material which includes one or more of: Cu, Ag, Al, or Au. In some embodiments, the method of forming the second structure comprises forming a material which includes one or more of: b-Ta, b-W, W, Pt, Cu doped with Iridium, Cu doped with Bismuth, or Cu doped an element of 3d, 4d, 5d, 4f, or 5f of periodic table groups.

[0095] At block 705, a third structure 206a/b is formed exhibiting magnetoelectric properties, wherein the third structure is adjacent to the second magnet with semi-insulating or insulating properties. In some embodiments, the method of forming the third structure comprises forming a material which includes one of: Cr, O, or multiferroic material, and wherein the multiferroic material comprises one or more of: Bi, Fe, O, Lu, or La.

[0096] In some embodiments, the method comprises: forming a first transistor and coupling it to the first magnet via a contact (e.g., 209a/b); controlling the first transistor by a switching signal; coupling the first transistor to a first supply having a first potential voltage; forming a second transistor coupling it to the first magnet via the contact; controlling the second transistor by the switching signal; and coupling the second transistor to a second supply having a second potential voltage, wherein the second potential voltage is higher than the first potential voltage, and wherein the first and second transistors are of different conductivity types.

[0097] Fig. 8 illustrates a smart device or a computer system or a SoC (System-on-

Chip) with MESO Logic, according to some embodiments. It is pointed out that those elements of Fig. 8 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0098] Fig. 8 illustrates a block diagram of an embodiment of a mobile device in which flat surface interface connectors could be used. In some embodiments, computing device 1600 represents a mobile computing device, such as a computing tablet, a mobile phone or smart-phone, a wireless-enabled e-reader, or other wireless mobile device. It will be understood that certain components are shown generally, and not all components of such a device are shown in computing device 1600.

[0099] In some embodiments, computing device 1600 includes first processor 1610 with MESO logic, according to some embodiments discussed. Other blocks of the computing device 1600 may also include a MESO logic, according to some embodiments. The various embodiments of the present disclosure may also comprise a network interface within 1670 such as a wireless interface so that a system embodiment may be incorporated into a wireless device, for example, cell phone or personal digital assistant. [00100] In some embodiments, processor 1610 can include one or more physical devices, such as microprocessors, application processors, microcontrollers, programmable logic devices, or other processing means. The processing operations performed by processor 1610 include the execution of an operating platform or operating system on which applications and/or device functions are executed. The processing operations include operations related to I/O (input/output) with a human user or with other devices, operations related to power management, and/or operations related to connecting the computing device 1600 to another device. The processing operations may also include operations related to audio I/O and/or display I/O.

[00101] In some embodiments, computing device 1600 includes audio subsystem 1620, which represents hardware (e.g., audio hardware and audio circuits) and software (e.g., drivers, codecs) components associated with providing audio functions to the computing device. Audio functions can include speaker and/or headphone output, as well as microphone input. Devices for such functions can be integrated into computing device 1600, or connected to the computing device 1600. In one embodiment, a user interacts with the computing device 1600 by providing audio commands that are received and processed by processor 1610.

[00102] In some embodiments, computing device 1600 comprises display subsystem 1630. Display subsystem 1630 represents hardware (e.g., display devices) and software (e.g., drivers) components that provide a visual and/or tactile display for a user to interact with the computing device 1600. Display subsystem 1630 includes display interface 1632, which includes the particular screen or hardware device used to provide a display to a user. In one embodiment, display interface 1632 includes logic separate from processor 1610 to perform at least some processing related to the display. In one embodiment, display subsystem 1630 includes a touch screen (or touch pad) device that provides both output and input to a user.

[00103] In some embodiments, computing device 1600 comprises I/O controller 1640. I/O controller 1640 represents hardware devices and software components related to interaction with a user. I/O controller 1640 is operable to manage hardware that is part of audio subsystem 1620 and/or display subsystem 1630. Additionally, I/O controller 1640 illustrates a connection point for additional devices that connect to computing device 1600 through which a user might interact with the system. For example, devices that can be attached to the computing device 1600 might include microphone devices, speaker or stereo systems, video systems or other display devices, keyboard or keypad devices, or other I/O devices for use with specific applications such as card readers or other devices. [00104] As mentioned above, I/O controller 1640 can interact with audio subsystem 1620 and/or display subsystem 1630. For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of the computing device 1600. Additionally, audio output can be provided instead of, or in addition to display output. In another example, if display subsystem 1630 includes a touch screen, the display device also acts as an input device, which can be at least partially managed by I/O controller 1640. There can also be additional buttons or switches on the computing device 1600 to provide I/O functions managed by I/O controller 1640.

[00105] In some embodiments, I/O controller 1640 manages devices such as accelerometers, cameras, light sensors or other environmental sensors, or other hardware that can be included in the computing device 1600. The input can be part of direct user interaction, as well as providing environmental input to the system to influence its operations (such as filtering for noise, adjusting displays for brightness detection, applying a flash for a camera, or other features).

[00106] In some embodiments, computing device 1600 includes power management 1650 that manages battery power usage, charging of the battery, and features related to power saving operation. Memory subsystem 1660 includes memory devices for storing information in computing device 1600. Memory can include nonvolatile (state does not change if power to the memory device is interrupted) and/or volatile (state is indeterminate if power to the memory device is interrupted) memory devices. Memory subsystem 1660 can store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of the applications and functions of the computing device 1600.

[00107] Elements of embodiments are also provided as a machine-readable medium (e.g., memory 1660) for storing the computer-executable instructions (e.g., instructions to implement any other processes discussed herein). The machine-readable medium (e.g., memory 1660) may include, but is not limited to, flash memory, optical disks, CD-ROMs, DVD ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, phase change memory (PCM), or other types of machine-readable media suitable for storing electronic or computer- executable instructions. For example, embodiments of the disclosure may be downloaded as a computer program (e.g., BIOS) which may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals via a communication link (e.g., a modem or network connection). [00108] In some embodiments, computing device 1600 comprises connectivity 1670. Connectivity 1670 includes hardware devices (e.g., wireless and/or wired connectors and communication hardware) and software components (e.g., drivers, protocol stacks) to enable the computing device 1600 to communicate with external devices. The computing device 1600 could be separate devices, such as other computing devices, wireless access points or base stations, as well as peripherals such as headsets, printers, or other devices.

[00109] Connectivity 1670 can include multiple different types of connectivity. To generalize, the computing device 1600 is illustrated with cellular connectivity 1672 and wireless connectivity 1674. Cellular connectivity 1672 refers generally to cellular network connectivity provided by wireless carriers, such as provided via GSM (global system for mobile communications) or variations or derivatives, CDMA (code division multiple access) or variations or derivatives, TDM (time division multiplexing) or variations or derivatives, or other cellular service standards. Wireless connectivity (or wireless interface) 1674 refers to wireless connectivity that is not cellular, and can include personal area networks (such as Bluetooth, Near Field, etc.), local area networks (such as Wi-Fi), and/or wide area networks (such as WiMax), or other wireless communication.

[00110] In some embodiments, computing device 1600 comprises peripheral connections 1680. Peripheral connections 1680 include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) to make peripheral connections. It will be understood that the computing device 1600 could both be a peripheral device ("to" 1682) to other computing devices, as well as have peripheral devices ("from" 1684) connected to it. The computing device 1600 commonly has a "docking" connector to connect to other computing devices for purposes such as managing (e.g., downloading and/or uploading, changing, synchronizing) content on computing device 1600. Additionally, a docking connector can allow computing device 1600 to connect to certain peripherals that allow the computing device 1600 to control content output, for example, to audiovisual or other systems.

[00111] In addition to a proprietary docking connector or other proprietary connection hardware, the computing device 1600 can make peripheral connections 1680 via common or standards-based connectors. Common types can include a Universal Serial Bus (USB) connector (which can include any of a number of different hardware interfaces), DisplayPort including MiniDisplayPort (MDP), High Definition Multimedia Interface (HDMI), Firewire, or other types. [00112] Reference in the specification to "an embodiment," "one embodiment," "some embodiments," or "other embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments. The various appearances of "an embodiment," "one embodiment," or "some embodiments" are not necessarily all referring to the same embodiments. If the specification states a component, feature, structure, or characteristic "may," "might," or "could" be included, that particular component, feature, structure, or characteristic is not required to be included. If the specification or claim refers to "a" or "an" element, that does not mean there is only one of the elements. If the specification or claims refer to "an additional" element, that does not preclude there being more than one of the additional element.

[00113] Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment anywhere the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

[00114] While the disclosure has been described in conjunction with specific embodiments thereof, many alternatives, modifications and variations of such embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. The embodiments of the disclosure are intended to embrace all such alternatives, modifications, and variations as to fall within the broad scope of the appended claims.

[00115] In addition, well known power/ground connections to integrated circuit (IC) chips and other components may or may not be shown within the presented figures, for simplicity of illustration and discussion, and so as not to obscure the disclosure. Further, arrangements may be shown in block diagram form in order to avoid obscuring the disclosure, and also in view of the fact that specifics with respect to implementation of such block diagram arrangements are highly dependent upon the platform within which the present disclosure is to be implemented (i.e., such specifics should be well within purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the disclosure, it should be apparent to one skilled in the art that the disclosure can be practiced without, or with variation of, these specific details. The description is thus to be regarded as illustrative instead of limiting. [00116] The following examples pertain to further embodiments. Specifics in the examples may be used anywhere in one or more embodiments. All optional features of the apparatus described herein may also be implemented with respect to a method or process.

[00117] Example 1. An apparatus comprising: a first magnet with conductive properties; a first structure adjacent to the first magnet; a second magnet with semi-insulative or insulative properties, wherein the second magnet is adjacent to the first structure; a second structure, a portion of which is adjacent to the first magnet, wherein the second structure comprises a spin orbit material; and a third structure with magnetoelectric properties, wherein the third structure is adjacent to the second magnet.

[00118] Example 2. The apparatus of claim 1, wherein the second magnet comprises a material which includes one or more of: Co, Fe, Ni, or O.

[00119] Example 3. The apparatus of claim 1, wherein the first magnet is one of a paramagnet or ferromagnet.

[00120] Example 4. The apparatus according to any one of claims 1 to 3, wherein the first magnet comprises a material which includes one or more of: Pt, Pd, W, Ce, Al, Li, Mg, Na, Cr, O, Co, Dy, Er, Eu, Gd, Fe, Nd, K, Pr, Sm, Tb, Tm, or V.

[00121] Example 5. The apparatus according to any one of claims 1 to 3, wherein the first magnet comprises one or a combination of materials which includes one or more of: a Heusler alloy, Co, Fe, Ni, Gd, B, Ge, Ga, permalloy, or Yttrium Iron Garnet (YIG), and wherein the Heusler alloy is a material which includes one or more of: Cu, Mn, Al, In, Sn, Ni, Sb, Ga, Co, Fe, Si, Pd, Sb, Si, V, or Ru.

[00122] Example 6. The apparatus according to any one of claims 1 to 3, wherein the second structure comprises: a fourth structure comprising Ag, wherein the fourth structure is adjacent to the first magnet; and a fifth structure including one of: Bi or W, wherein the fifth structure is adjacent to the first magnet and to a conductor.

[00123] Example 7. The apparatus of claim 6, wherein the conductor comprises a material which includes one or more of: Cu, Ag, Al, or Au.

[00124] Example 8. The apparatus of claim 1, wherein the third structure comprises a material which includes one of: Cr, O, or multiferroic material, and wherein the multiferroic material comprises one or more of: Bi, Fe, O, Lu, or La.

[00125] Example 9. The apparatus according to any one of claims 1 to 8, wherein the second structure comprises a material which includes one or more of: b-Ta, b-W, W, Pt, Cu doped with Iridium, Cu doped with Bismuth, or Cu doped an element of 3d, 4d, 5d, 4f, or 5f of periodic table groups. [00126] Example 10. The apparatus of claim 1 comprises: a first transistor coupled to the first magnet via a contact, wherein the first transistor is controllable by a switching signal, and wherein the first transistor is coupled to a first supply having a first potential voltage; and a second transistor coupled to the first magnet via the contact, wherein the second transistor is controllable by the switching signal, and wherein the second transistor is coupled to a second supply having a second potential voltage, wherein the second potential voltage is higher than the first potential voltage, and wherein the first and second transistors are of different conductivity types.

[00127] Example 11. The apparatus of claim 1, wherein the first and second magnets have in-plane magnetic anisotropy.

[00128] Example 12. The apparatus of claim 1, wherein the first structure comprises one or more of: Ru, Os, Hs, Fe, or other transition metals from a platinum group of the periodic table.

[00129] Example 13. An apparatus comprising: an input side comprising an apparatus according to any one of claims 1 to 12; an output side comprising an apparatus according to any one of claims 1 to 12; a first conductor adjacent to the third structure of the apparatus of the input side, wherein the first conductor is to provide an input charge current; a second conductor adjacent to a portion of the second structure of the input side and also adjacent to the third structure of the apparatus of the output side; and a fourth conductor adjacent to the third structure of the apparatus of the output side, wherein the fourth conductor is to provide an output charge current.

[00130] Example 14. The apparatus of claim 13, wherein the first, second, and third conductors include one or more of: Cu, Ag, Al, or Au.

[00131] Example 15. A system comprising: a memory; a processor coupled to the memory, the processor including an apparatus according to any one of apparatus claims 1 to 12 or apparatus claim 13 to 14; and a wireless interface to allow the processor to

communicate with another device.

[00132] Example 16. An apparatus comprising: a first input side comprising an apparatus according to any one of claims 1 to 12; a second input side comprising an apparatus according to any one of claims 1 to 12; a third input side comprising an apparatus according to any one of claims 1 to 12; an output side comprising an apparatus according to any one of claims 1 to 12; first, second, and third conductors adjacent to the third structures of the apparatuses of the first, second and third input sides, respectively, wherein the first, second, and third conductors are to provide first, second and third input charge currents, respectively; fourth, fifth, and sixth conductors adjacent to a portion of the second structures of the apparatuses of the first, second, and third input sides, respectively; a seventh conductor adjacent to portions of the fourth, fifth, and sixth conductors, wherein the seventh conductor is also adjacent to the third structure of the apparatus of the output side; and an eighth conductor adjacent to a portion of the second structure of the apparatus of the output side, wherein the eighth conductor is to provide an output charge current.

[00133] Example 17. A method comprising: forming a first magnet with conductive properties; forming a first structure adjacent to the first magnet; forming a second magnet with semi-insulative or insulative properties, wherein the second magnet is adjacent to the first structure; forming a second structure, a portion of which is adjacent to the first magnet, wherein the second structure is to provide an inverse spin-orbit coupling effect; and forming a third structure with magnetoelectric properties, wherein the third structure is adjacent to the second magnet.

[00134] Example 18. The method of claim 17, wherein forming the second magnet comprises forming a material which includes one or more of: Co, Fe, Ni, or O.

[00135] Example 19. The method of claim 17, wherein forming the first magnet comprises forming one of a paramagnet or ferromagnet.

[00136] Example 20. The method according to any one of claims 17 to 19, wherein forming the first magnet comprises forming a material which includes one or more of: Pt, Pd, W, Ce, Al, Li, Mg, Na, Cr, O, Co, Dy, Er, Eu, Gd, Fe, Nd, K, Pr, Sm, Tb, Tm, or V.

[00137] Example 21. The method according to any one of claims 17 to 19, wherein forming the first magnet comprises forming one or a combination of materials which includes one or more of: a Heusler alloy, Co, Fe, Ni, Gd, B, Ge, Ga, permalloy, or Yttrium Iron Garnet (YIG), and wherein the Heusler alloy is a material which includes one or more of: Cu, Mn,

Al, In, Sn, Ni, Sb, Ga, Co, Fe, Si, Pd, Sb, Si, V, or Ru.

[00138] Example 22. The method according to any one of claims 17 to 19, wherein forming the second structure comprises: forming a fourth structure comprising Ag, wherein the fourth structure is adjacent to the first magnet; and forming a fifth structure including one of: Bi or W, wherein the fifth structure is adjacent to the first magnet and to a conductor.

[00139] Example 23. The method of claim 22, wherein forming the conductor comprises forming a material which includes one or more of: Cu, Ag, Al, or Au.

[00140] Example 24. The method of claim 17, wherein forming the third structure comprises forming a material which includes one of: Cr, O, or multiferroic material, and wherein the multiferroic material comprises one or more of: Bi, Fe, O, Lu, or La. [00141] Example 25. The method according to any one of claims 17 to 24, wherein forming the second structure comprises forming a material which includes one or more of: b- Ta, b-W, W, Pt, Cu doped with Iridium, Cu doped with Bismuth, or Cu doped an element of 3d, 4d, 5d, 4f, or 5 f of periodic table groups.

[00142] Example 26. The method of claim 17 comprises: forming a first transistor and coupling it to the first magnet via a contact; controlling the first transistor by a switching signal; coupling the first transistor to a first supply having a first potential voltage; forming a second transistor coupling it to the first magnet via the contact; controlling the second transistor by the switching signal; and coupling the second transistor to a second supply having a second potential voltage, wherein the second potential voltage is higher than the first potential voltage, and wherein the first and second transistors are of different conductivity types.

[00143] Example 27. The method of claim 17, wherein the first and second magnets have in-plane magnetic anisotropy.

[00144] Example 28. The method of claim 17, wherein the first structure comprises one or more of: Ru, Os, Hs, Fe, or other transition metals from a platinum group of the periodic table.

[00145] An abstract is provided that will allow the reader to ascertain the nature and gist of the technical disclosure. The abstract is submitted with the understanding that it will not be used to limit the scope or meaning of the claims. The following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.