BACKGROUND

[0001] Spintronics is the study of intrinsic spin of the electron and its associated magnetic moment in solid-state devices. Spintronic logic are integrated circuit devices that use a physical variable of magnetization or spin as a computation variable. Such variables can be non-volatile (e.g., preserving a computation state when the power to an integrated circuit is switched off). Non-volatile logic can improve the power and computational efficiency by allowing architects to put a processor to un-powered sleep states more often and therefore reduce energy consumption. Existing spintronic logic generally suffer from high energy and relatively long switching times.

[0002] For example, large write current (e.g., greater than 100 μΑ/bit) and voltage

(e.g., greater than 0.7 V) are needed to switch a magnet (i.e., to write data to the magnet) in Magnetic Tunnel Junctions (MTJs). Existing Magnetic Random Access Memory (MRAM) based on MTJs also suffer from high write error rates (WERs) or low speed switching. For example, to achieve lower WERs, switching time is slowed down which degrades the performance of the MRAM. MTJ based MRAMs also suffer from reliability issues due to tunneling current in the spin filtering tunneling dielectric of the MTJs e.g., magnesium oxide (MgO).

BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The embodiments of the disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure, which, however, should not be taken to limit the disclosure to the specific embodiments, but are for explanation and understanding only.

[0004] Fig. 1A illustrates hysteresis plot showing a piezoelectric ferroelectric polarization vs. voltage applied across a material via two electrodes.

[0005] Fig. IB illustrates hysteresis plot showing a piezoelectric ferroelectric polarization vs. voltage applied across the material of Fig. 1A after switching positions of the two electrodes.

[0006] Fig. 2 illustrates a magnetostrictive spin orbit (MESO) logic with unipolar piezoelectric stack, according to some embodiments of the disclosure. [0007] Fig. 3A illustrates a spin orbit material stack at the input of an interconnect producing charge current from spins polarized in a first direction, according to some embodiments of the disclosure.

[0008] Fig. 3B illustrates a spin orbit material stack at the input of the interconnect producing zero charge current from spins polarized in a second direction, according to some embodiments of the disclosure.

[0009] Figs. 4A-B illustrate two logic states of MESO logic, respectively, operable as an inverter, according to some embodiments.

[0010] Fig. 5 illustrates a top view of a layout of the MESO logic, according to some embodiments.

[0011] Fig. 6 illustrates a majority gate using MESO logic devices, according to some embodiments.

[0012] Fig. 7 illustrates a top view of a layout of the majority gate of Fig. 6,

according to some embodiments.

[0013] Fig. 8 illustrates a MESO inverter with a different layout but the same functionality as inverter, according to some embodiments.

[0014] Fig. 9 illustrates a MESO repeater/buffer accomplished in just one stage rather than two, according to some embodiments.

[0015] Fig. 10 illustrates a smart device or a computer system or a SoC (System-on-

Chip) with MESO logic, according to some embodiments.

DETAILED DESCRIPTION

[0016] Spin polarized current is generally conducted between nanomagnets to switch magnetization by spin torque effect. In this and multiple other spintronic devices, the signal is sent from one node to the other as a spin quantity (e.g., spin polarized current, a domain wall, or a spin wave). These signals are slow (e.g., 1000 m/s) and exponentially attenuate over the length of the interconnect (e.g., 1 μηι). Various embodiments describe a logic device in which the signal is sent over an electrical interconnect. The charge current does not attenuate and the communication is much faster (e.g., limited by the RC delay of the interconnect). Generally, current induced injection of spin current from a magnet is used as the charge-to-spin conversion, and spin torque is used to switch magnetization in the output magnet. In such a case, the effect of magnetoresistance detected by a sense amplifier is used as the spin-to-charge conversion. Due to much more efficient conversion mechanisms, the switching time of the logic device of various embodiments is faster than general spin logic devices (e.g., 100 ps vs. 1 ns). The switching energy of the logic device of various embodiments is also lower than general spin logic devices (e.g., 10 aJ vs. 100 fj).

[0017] Various embodiments use magnetostrictive effect to improve logic efficiency.

Magnetostrictive effect has the ability to manipulate the magnetization (and the associated spin of electrons in the material) by an applied electric field. Since an estimated energy dissipation per unit area per magnet switching event through the magnetostrictive effect is an order of magnitude smaller than with spin-transfer torque (STT) effect, materials exhibiting magnetostrictive effect have the capability for next-generation memory and logic applications.

[0018] Various embodiments describe a Magnetostrictive Spin Orbit Logic (MESO) which is a combination of various physical phenomena for spin-to-charge and charge-to-spin conversion. In some embodiments, a MESO device is provided which uses strain based magnetoelectric logic. Strain based magnetoelectric logic is a robust switching mechanism which is less prone to interface effects. Using magnetostrictive effect allows the use of hybrid magnetostrictive material stacks.

[0019] In some embodiments, spin-to-charge conversion is achieved via a layer with the inverse Rashba-Edelstein effect (or inverse spin Hall effect) wherein a spin current injected from an input magnet produces a charge current. The sign of the charge current is determined by the direction of the injected spin and thus of magnetization. In some embodiments, spin-to-charge transduction of a 90 degree switching magnet is obtained by vector projection of the converted charge currents.

[0020] In some embodiments, charge-to-spin conversion is achieved via ferroelectric switching which produces a strain response in the ferroelectric. In some embodiments, ferromagnet or paramagnet used for state retention (via magneto-elasticity) has two stable states located perpendicular to each other. For example, the ferromagnet or paramagnet can have perpendicular magnetization (e.g., +/- z direction) for one state and in-plane magnetization (+/- x direction) for another state. The stability in the magnetizations is obtained from piezoelectric strain and/or from the demagnetization and anisotropy of the magnet, in accordance with some embodiments. In some embodiments, the readout of the two stable states is presence of charge current or no charge current. In some embodiments, the material stack providing magnetostrictive effect uses ferro-electricity or ferromagnetism as the primary retention mechanism. Ferroelectric is unipolar due to the presence of the internal fields. [0021] There are many technical effects of the various embodiments. For example, high speed operation of the logic (e.g., 100 picoseconds (ps)) is achieved via the use of magnetoelectric switching operating on nanomagnets. In some examples, switching energy is reduced (e.g., 1-10 attojoules (aJ)) because the current needs to be "on" for a shorter time (e.g., approximately 3 ps) in order to charge the capacitor. In some examples, in contrast to the spin current, here charge current does not attenuate when it flows through an interconnect. The MESO device of some embodiments improves the speed of the response of nanomagnets by using magnetostrictive switching mechanism. Other technical effects will be evident from the various embodiments and figures.

[0022] In the following description, numerous details are discussed to provide a more thorough explanation of embodiments of the present disclosure. It will be apparent, however, to one skilled in the art, that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring embodiments of the present disclosure.

[0023] Note that in the corresponding drawings of the embodiments, signals are represented with lines. Some lines may be thicker, to indicate more constituent signal paths, and/or have arrows at one or more ends, to indicate primary information flow direction. Such indications are not intended to be limiting. Rather, the lines are used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit or a logical unit. Any represented signal, as dictated by design needs or preferences, may actually comprise one or more signals that may travel in either direction and may be implemented with any suitable type of signal scheme.

[0024] Throughout the specification, and in the claims, the term "connected" means a direct connection, such as electrical, mechanical, or magnetic connection between the things that are connected, without any intermediary devices. The term "coupled" means a direct or indirect connection, such as a direct electrical, mechanical, or magnetic connection between the things that are connected or an indirect connection, through one or more passive or active intermediary devices. The term "circuit" or "module" may refer to one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data/clock signal. The meaning of "a," "an," and "the" include plural references. The meaning of "in" includes "in" and "on." [0025] The terms "substantially," "close," "approximately," "near," and "about," generally refer to being within +/- 10% of a target value (unless specifically specified).

Unless otherwise specified the use of the ordinal adjectives "first," "second," and "third," etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.

[0026] For the purposes of the present disclosure, phrases "A and/or B" and "A or B" mean (A), (B), or (A and B). For the purposes of the present disclosure, the phrase "A, B, and/or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0027] For purposes of the embodiments, the transistors in various circuits and logic blocks described here are metal oxide semiconductor (MOS) transistors or their derivatives, where the MOS transistors include drain, source, gate, and bulk terminals. The transistors and/or the MOS transistor derivatives also include Tri-Gate and FinFET transistors, Gate All Around Cylindrical Transistors, Tunneling FET (TFET), Square Wire, or Rectangular Ribbon Transistors, ferroelectric FET (FeFETs), or other devices implementing transistor functionality like carbon nanotubes or spintronic devices. MOSFET symmetrical source and drain terminals i.e., are identical terminals and are interchangeably used here. A TFET device, on the other hand, has asymmetric Source and Drain terminals. Those skilled in the art will appreciate that other transistors, for example, Bi-polar junction transistors— BJT PNP/NPN, BiCMOS, CMOS, eFET, etc., may be used without departing from the scope of the disclosure. The term "MN" indicates an n-type transistor (e.g., NMOS, NPN BJT, etc.) and the term "MP" indicates a p-type transistor (e.g., PMOS, PNP BJT, etc.).

[0028] Fig. 1A illustrates hysteresis plot 100 showing a piezoelectric ferroelectric polarization vs. voltage applied voltage across a material via two electrodes, and a stack of layers which additionally includes a ferromagnet, the magnetization of which is affected by strain thus exhibiting magnetostrictive effect.

[0029] In some embodiments, the material stack used for generating plot 100 include layers 105, 106, 107, and 108. In some embodiments, layer 105 is a first electrode comprising Sr and Ru. In some embodiments, layer 105 comprises conductive oxide and/or conductive nitride. In some embodiments, layer 105 comprises strontium ruthenate (SRO) which is an oxide of strontium and ruthenium (Sr2Ru04).

[0030] In some embodiments, layer 106 comprises a piezoelectric (PZE) material. In some embodiments, PZE material is PMN-PT (lead magnesium niobate-lead titanate). PMN- PT is a ferroelectric which has the highest value of PZE coefficient. Other PZE materials that can be used for layer 106 are lead zirconate titanate Pb[Zr _x Tii- _x ]0 ₃ (PZT), barium titanate BaTiCb (BTO), Pb(ZnxNbi- _x )03-PbTi03 (PZN-PT), BiFeCb (BFO), polyvinylidene difluoride (PVDF), sodium potassium niobate ((K,Na)Nb0 ₃ ), in accordance with some embodiments. In some embodiments, layer 106 is unipolar in that it is to switch between zero volts and a positive value, or zero volts and a negative value.

[0031] In some embodiments, layer 107 is a second electrode which is a metal (e.g., platinum). In some embodiments, layer 108 is a magnet (e.g., a ferromagnet or paramagnet) which can have in-plane or out-of-plane magnetizations. In some embodiments, when voltage is applied across the first and second electrodes, charge-to-spin conversion is achieved via PZE layer 106 switching its strain value which produces a stress in the magnet 108 and changes its anisotropy (e.g. energies of configurations with in-plane and out-of-plane magnetizations). Ferroelectric is unipolar (e.g., switching at voltage values of the same sign) due to the presence of the internal fields caused by different electrodes on its two sides.

[0032] With reference to plot 100, the x-axis is voltage across layers 108 and 107 and the y-axis is polarization of PZE layer 106. The polarization is symmetrical around the zero point along the y-axis. Plot 100 shows two parts of the hysteretic curve, curve 101 for negative polarization and curve 102 for positive polarization. Curve 101 can correspond to strain such that in-plane magnetization of magnet 108 is stable, while curve 102 can correspond to strain such that out-of-plane (or perpendicular to the plane of the magnet) magnetization of magnet 108 is stable (so called easy axis). The PZE layer 106 across which voltage is applied experiences strain and causes magnetostrictive response to stress.

[0033] Magnetostrictive effect is a property of magnetic material that causes the material to change its energy when stress is applied to the magnetic material.

Magnetostrictive effect is a kind of magnetoelectric effect and has a preferred axis but not in the preferred direction along an x/y axis. So, magnetoelectric effect may not reverse magnetization direction of magnet 108, but it switches the magnetization of magnet 108 from in-plane to perpendicular magnetization. In some embodiments, in the absence of strain, the magnetization (or polarization) of magnet 108 points along its easy axis (e.g., in-plane) as shown by curve 101. When strain is applied to magnet 108, the anisotropy of magnet 108 adjusts so that the easy axis is out-of-plane as shown by curve 102.

[0034] Fig. IB illustrates hysteresis plot 120 showing hysteresis shift in magnet polarization behavior with applied voltage across the material of Fig. 1A after switching positions of the two electrodes. It is pointed out that those elements of Fig. IB having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0035] Plot 120 shows two curves, 121 and 122. Plot 120 shows two parts of the hysteretic curve, curve 121 for negative polarization and curve 122 for positive polarization. Curve 121 can correspond to strain such that in-plane magnetization of magnet 108 is stable, while curve 122 can correspond to strain such that out-of-plane (or perpendicular to the plane of the magnet) magnetization of magnet 108 is stable (so called easy axis). While curves 121 and 122 may appear similar to curves 101 and 102, respectively, curves 101 and 102 are shifted along the x-axis. The shift along the axis is because of the switching of the positions of the first and second electrodes 105 and 107 of Fig. IB compared to the positions of the first and second electrodes 105 and 107 of Fig. 1A.

[0036] Fig. 2 illustrates MESO logic 200 with unipolar piezoelectric stack, according to some embodiments of the disclosure. It is pointed out that those elements of Fig. 2 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0037] In some embodiments, MESO logic 200 comprises first magnet 201, a stack of layers (e.g., layers 202a/b, 203a/b, and 204a/b, respectively) to provide spin orbit coupling one of which is/are adjacent to first magnet 201, interconnecting conductor 205 (e.g., a non- magnetic charge conductor), one of more layers to provide magnetostrictive effect (e.g., layers 206a/b and 207), and second magnet 208.

[0038] In some embodiments, first and second magnets 201 and 208 are paramagnets.

In some embodiments, the materials for first and second paramagnets 201 and 207 have saturated magnetization M _s and effective anisotropy field Hk. Saturated magnetization M _s is generally the state reached when an increase in applied external magnetic field H cannot increase the magnetization of the material. Anisotropy Hk generally refers material properties that are highly directionally dependent. In some embodiments, materials for first and second paramagnets 201 and 208 are non-ferromagnetic elements with strong paramagnetism which have high number of unpaired spins but are not room temperature ferromagnets.

[0039] In some embodiments, first and second paramagnets 201 and 208 comprise a material which includes one or more of: Platinum(Pt), Palladium (Pd), Tungsten (W), Cerium (Ce), Aluminum (Al), Lithium (Li), Magnesium (Mg), Sodium (Na), CnCb (chromium oxide), CoO (cobalt oxide), Dysprosium (Dy), Dy20 (dysprosium oxide), Erbium (Er), Er ₂ Cb (Erbium oxide), Europium (Eu), EU2O3 (Europium oxide), Gadolinium (Gd), Gadolinium oxide (Gd203), FeO and Fe203 (Iron oxide), Neodymium (Nd), Nd2C (Neodymium oxide), KO2 (potassium superoxide), praseodymium (Pr), Samarium (Sm), SrmC (samarium oxide), Terbium (Tb), Tb2Cb (Terbium oxide), Thulium (Tm), TrroCb (Thulium oxide), and V2O3 (Vanadium oxide). In some embodiments, the first and second paramagnets 201 and 208 comprise dopants which include one of: Ce, Cr, Mn, Nb, Mo, Tc, Re, Nd, Gd, Tb, Dy, Ho, Er, Tm, or Yb.

[0040] In some embodiments, first and second magnets 201 and 208 are

ferromagnets. In some embodiments, first and second magnets 201 and 208 are free ferromagnets that are made from CFGG (i.e., Cobalt (Co), Iron (Fe), Germanium (Ge), or Gallium (Ga) or a combination of them). Here, free magnets refer to magnets whose magnetization can change by a stimulus (e.g., stress, strain, exchange bias, etc.). In some embodiments, first and second magnets 201 and 208 are free magnets that are formed from Heusler alloy(s). Heusler alloy is ferromagnetic metal alloy based on a Heusler phase.

Heusler phase is intermetallic with certain composition and face-centered cubic (FCC) crystal structure. The ferromagnetic property of the Heusler alloy is a result of a double-exchange mechanism between neighboring magnetic ions.

[0041] In some embodiments, first and second magnets 201 and 208 are Heusler alloy lattices matched to Ag (e.g., the Heusler alloy is engineered to have a lattice constant close (e.g., within 3%) to that of Ag or to a rotated lattice). In some embodiments, the direction of the spin polarization is determined by the magnetization direction of first magnet 201. In some embodiments, the magnetization direction of second magnet 208 depends on the direction of the strain provided by layer 206a/b, which in turn depends on the direction of an input charge current Icharge (IN).

[0042] In some embodiments, first and second magnets 201 and 208 are formed of

Heusler alloy, Co, Fe, Ni, Gd, B, Ge, Ga, or a combination of them. In some embodiments, Heusler alloys that form first and second magnets 201 and 207 include one of: Cu ₂ MnAl, Cu ₂ MnIn, Cu ₂ MnSn, Ni ₂ MnAl, Ni ₂ MnIn, Ni ₂ MnSn, Ni ₂ MnSb, Ni ₂ MnGa Co ₂ MnAl,

Co ₂ MnSi, Co ₂ MnGa, CoJVInGe, Pd ₂ MnAl, Pd ₂ MnIn, PdJVInSn, PdJVInSb, Co ₂ FeSi, Co ₂ FeAl, Fe ₂ VAl, Mn ₂ VGa, Co ₂ FeGe, MnGa, or MnGaRu.

[0043] In some embodiments, conductor 205 (or charge interconnect) is coupled to at least a portion of the stack of layers and layer 206a. For example, conductor 205 is coupled to layer 204a of the stack. In some embodiments, the stack of layers is to provide an inverse Rashba-Edelstein effect (or inverse spin Hall effect). The stack of layers here is also referred to as the spin-to-charge conversion module. In some embodiments, the stack of layers provides spin-to-charge conversion where a spin current/? (or spin energy J _s ) is injected from first magnet 201 (also referred to as the input magnet) and charge current Ic is generated by the stack of layers. This charge current Ic is provided to conductor 205 (e.g., charge interconnect). In contrast to spin current, charge current does not attenuate in conductor 205. The direction of the charge current I _c depends on the direction of magnetization of first magnet 201. In some embodiments, the charge current I _c develops a potential difference across layers 206a/207a and magnet 208, and switches the polarization of magnet 208. In some embodiments, layers 206a/207a exert stress on second magnet layer 208, and determines the magnetization of second magnet 208 as discussed with reference to Figs. 1A- B

[0044] In some embodiments, layers 206a/b and 207a/b provide strain which exerts stress and provides the magnetostrictive effect to switch the magnets 208/201, respectively. For example, layers 206b/207b provide magnetostrictive effect to switch first magnet 201, while layers 206a/207a provide magnetostrictive effect to switch second magnet 208.

[0045] While the various embodiments of Fig. 2 illustrates two layers 206a/b and

207a/b to provide magnetostrictive effect, a single layer or more than two layers can also be used. For example, if the magnet 201 is conductive enough and has a suitable value of internal field at the interface with the ferroelectric, it can assume the role of electrode 207b.

[0046] In some embodiments, layer 207a/b is a first electrode comprising Sr and Ru.

In some embodiments, layer 207a/b comprises strontium ruthenate (SRO) which is an oxide of strontium and ruthenium (Sr2Ru04). In some embodiments, layer 206a/b comprises a PZE material. In some embodiments, PZE material is PMN-PT (lead magnesium niobate-lead titanate). PMN-PT is a ferroelectric which has the highest value of PZE coefficient. Other PZE materials that can be used for layer 206a/b are lead zirconate titanate Pb[Zr _x Tii- _x ]0 ₃ (PZT), barium titanate BaTiCb (BTO), Pb(ZnxNbi-x)03-PbTi03 (PZN-PT), BiFeCb (BFO), polyvinylidene difluoride (PVDF), sodium potassium niobate ((K,Na)Nb0 ₃ ). In some embodiments, layer 206a/b is a unipolar PZE in that is operates between 0 V and a positive value, or 0 V and a negative valye.

[0047] In some embodiments, layer 205 is a second electrode which is a metal (e.g., platinum, copper, etc.). In some embodiments, layer 205 is an interconnect which is unipolar in that it carries a signal with voltage swing between 0 V or a positive value, or 0 V or a negative value. In some embodiments, layers 206a/b and 207a/b together are PZE materials in which strain can be switched by, for example, greater than 100 ppm. In some

embodiments, layers 206a/b and 207a/b together are unipolar ferroelectrics engineered with internal fields that provide the strain on magnets 201 and 208 to switch their magnetizations between in-plane and perpendicular magnetizations. In some embodiments, layers 206a/b and 207a/b together are magnetostrictive materials with respond to strain via change in magnetic anisotropy.

[0048] In some embodiments, layer 206a/b forms ferro-elastic nodes which comprise a material which includes one of: lead zirconate titanate Pb[Zr _x Tii- _x ]0 ₃ (PZT), barium titanate BaTiCb (BTO), Pb(Zn _x Nbi- _x )0 ₃ -PbTi0 ₃ (PZN-PT), BiFe0 ₃ (BFO), polyvinylidene difluoride (PVDF), sodium potassium niobate ((K,Na)Nb0 ₃ ). Other examples for materials used for layer 206a/b include: BFO (Bismuth ferrite) class of perovskites, tetragonal zirconia, or LCO (Lanthanum Cobaltite) class of perovskites. In some embodiments, the BFO class of perovskites includes one of: Bi, Fe, O, Lu, La, or Ce. In some embodiments, the BFO class of perovskites includes one of: BiFe0 ₃ , LuFe02, LuFe204, La doped BiFe0 ₃ , or Ce doped BiFe0 ₃ . In some embodiments, the LCO class of perovskites includes one of: Ba, Sr, Co, Fe, O, or La. In some embodiments, the LCO class of perovskites includes one of:

Bao.5Sro.5Coo.8Feo.20 ₃ -sigma ΟΓ Lao.58Sro.4Co0.2Feo.80 ₃ -sigma.

[0049] In some embodiments, layer 207a/b forms magnetostrictive nodes which comprise one or more elements: Fe, Ga, Ci, or Ge. In some embodiments, layer 207a/b comprises one of: FeGa, Terfenol-D, FeGa and CoFeGa derivatives, Co2FeGa, or

Co2FeGeGa and derivatives.

[0050] In this example, the length of first magnet is L _m , the width of conductor 205 is

Wc, the length of conductor 205 from the interface of layer 204 to layer 206a is L _c , t _c is the thickness of the magnets 201 and 208, and ΪΜΕ is the thickness of layer 206a. In some embodiments, conductor 205 comprises a material including one of: Cu, Ag, Al, or Au. In some embodiments, both magnets 201 and 208 have the same thickness and/or width. In some embodiments, magnets 201 and 208 may have different thickness and/or widths.

[0051] In some embodiments, the input and output charge conductors (21 la and

211b, respectively) and associated spin-to-charge and charge-to-spin converters are provided. In some embodiments, input charge current Icharge(iN) is provided on interconnect 21 la (e.g., charge interconnect made of same material as interconnect 205). In some embodiments, interconnect 21 la is coupled to first magnet 201 via layer 206b. In some embodiments, interconnect 21 la is orthogonal to first magnet 201. For example, interconnect 211a extends in the +x direction while first magnet 201 extends in the -y direction. In some embodiments, Icharge(iN) is converted to corresponding magnetic polarization of 201 by layer 206b.

[0052] In some embodiments, an output interconnect 21 lb is provided to transfer output charge current I _C har _g e(2) to another logic or stage. In some embodiments, output interconnect 21 lb is coupled to second magnet 208 via a stack of layers that exhibit spin Hall effect and/or Rashba Edelstein effect. For example, layers 202b, 203b, and 204b are provided as a stack to couple output interconnect 21 1b with second magnet 208. Material wise, layers 202b, 203b, and 204b are formed of the same material as layers 202a, 203a, and 204a, respectively.

[0053] In some embodiments, a transistor (e.g., p-type transistor MPl) is coupled to magnet 201. In this example, the source terminal of MP l is coupled to a supply Vdd, the gate terminal of MPl is coupled to a control voltage Vci (e.g., a switching clock signal, which switches between Vdd and ground), and the drain terminal of MPl is coupled to magnet 201. In some embodiments, the current Idrfve from transistor MPl generates spin current into the stack of layers (e.g., layers 202a, 203a, and 204a).

[0054] In some embodiments, along with the p-type transistor MP l connected to Vdd

(or an n-type transistor connected to Vdd but with gate overdrive above Vdd), an n-type transistor MNl is provided which couples to magnet 201 , where the n-type transistor is operable to couple ground (or 0V) to magnet 201. In some embodiments, the n-type transistor MN2 is provided which is operable to couple ground (or 0V) to magnet 208.

[0055] In some embodiments, a p-type transistor MP2 is provided which is operable to couple power supply (Vdd or -Vdd) to magnet 208. For example, when clock is low (e.g., Vci=0 V), then transistor MP l is on and Vdd is coupled to magnet 201 (e.g., power supply is Vdd) and 0 V is coupled to magnet 208. This provides a potential difference for charge current to flow. Continuing with this example, when clock is high (e.g., V _c i=Vdd and power supply is Vdd), then transistor MPl is off, transistor MNl is on, and transistor MN2 is off. As such, 0 V is coupled to magnet 201 while Vdd is coupled to magnet 208.

[0056] In some embodiments, the power supply is a negative power supply (e.g., -

Vdd). In that case, the source of transistor MPl is connected to 0 V, and the source of transistor MNl is connected to -Vdd, and transistor MN2 is on. When Vd = 0V and power supply is -Vdd , then transistor MNl is on, and transistor MPl is off, and transistor MN2 (whose source is at -Vdd ) is off and transistor MP2 whose source is 0 V is on. In this case, - Vdd is coupled to input magnet 201 and 0 V is coupled to output magnet 208. This also provides a path for charge current to flow. Continuing with this example, when clock is high (e.g., Vd=-Vdd and power supply is -Vdd), then transistor MP l is off, transistor MNl is on, and transistor MN2 is off. As such, 0 V is coupled to input magnet 201.

[0057] In some embodiments, first magnet 201 injects a spin polarized current into the high spin-orbit coupling (SOC) material stack (e.g., layers 202a, 203a, and 204a). The spin polarization is determined by the magnetization of first magnet 201. In some embodiments, the stack comprises i) an interface 203 with a high density 2D (two dimensional) electron gas and with high SOC formed between 202 and 204 materials such as Ag or Bi, or ii) a bulk material 204 with high Spin Hall Effect (SHE) coefficient such as Ta, W, or Pt. In some embodiments, a spacer (or template layer) is formed between first magnet 201 and the injection stack. In some embodiments, this spacer is a templating metal layer which provides a template for forming first magnet 201. In some embodiments, the metal of the spacer which is directly coupled to first magnet 201 is a noble metal (e.g., Ag, Cu, or Au) doped with other elements from Group 4d and/or 5d of the Periodic Table. In some embodiments, first magnet 201 are sufficiently lattice matched to Ag (e.g., a material which is engineered to have a lattice constant close (e.g., within 3%) to that of Ag).

[0058] Here, sufficiently matched atomistic crystalline layers refer to matching of the lattice constant 'a' within a threshold level above which atoms exhibit dislocation which is harmful to the device (for instance, the number and character of dislocations lead to a significant (e.g., greater than 10%) probability of spin flip while an electron traverses the interface layer). For example, the threshold level is within 5% (e.g., threshold levels in the range of 0% to 5% of the relative difference of the lattice constants). As the matching improves (e.g., matching gets closer to perfect matching), spin injection efficiency from spin transfer from first magnet 201 to first ISHE/ISOC stacked layer increases. Poor matching (e.g., matching worse than 5%) implies dislocation of atoms that is harmful for the device.

[0059] Table 1 summarizes transduction mechanisms for converting magnetization to charge current and charge current to magnetization for bulk materials and interfaces.

Table 1: Transduction mechanisms for Spin to Charge and Charge to Spin Conversion

[0060] The following section describes the spin-to-charge and charge-to-spin dynamics. In some embodiments, the spin-orbit mechanism responsible for spin-to-charge conversion is described by the inverse Rashba-Edelstein effect in 2D electron gases. The Hamiltonian (energy) of spin-orbit coupling electrons in a 2D electron gas is:

H _R = a _R (kxz). σ where a _R is the Rashba-Edelstein coefficient, 'k' is the operator of momentum of electrons, z is a unit vector perpendicular to the 2D electron gas, and σ is the operator of spin of electrons.

[0061] The spin polarized electrons with direction of polarization in-plane (e.g., in the xy -plane) experience an effective magnetic field dependent on the spin direction:

a _R .

B (k)= — (fcxz)

½

where i _B is the Bohr magneton

[0062] This results in the generation of a charge current I _c (or Icharge(OUT)) in interconnect 205 proportional to the spin current Is (or J _s ). The spin-orbit interaction by Ag and Bi interface layers 202a/b and 204a/b (e.g., the Inverse Rashba-Edelstein Effect (IREE)) produces a charge current I _c in the horizontal direction given as:

where w _m is width of the input magnet 201, and λ _ΙΚΕΕ is the IREE constant (with units of length) proportional to a _R .

[0063] Alternatively, the Inverse Spin Hall Effect in Ta, W, or Pt layer 203a/b produces the horizontal charge current l _c given as:

. _ 0 _SHE t _SHE I _s

2w _m

[0064] Both IREE and ISHE effects produce spin-to-charge current conversion around 0.1 with existing materials at 10 nm (nanometers) magnet width. For scaled nanomagnets (e.g., 5 nm wide magnets) and exploratory SHE materials such as Bi2Se3, the spin-to-charge conversion efficiency can be between 1 and 2.5. The net conversion of the drive charge current Idnve to magnetization dependent charge current is given as:

j _± £k _for IREE and / _c = + ^Θ ™**™* ^ΡΙ * for ISHE

w _m 2w _m

where 'P' is the dimensionless spin polarization. For this estimate, the drive current Idnve and the charge current I _c = I _d = 100 μΑ is set. As such, when estimating the resistance of the ISHE interface to be equal to R = 100 Ω, then the induced voltage is equal to V _ISHE = 10 mV.

[0065] The charge current I _c , carried by interconnect 205, produces a voltage on the capacitor of ME layer 206a comprising ferro-elastic materials (e.g., perovskites with Co and Zr). For the following parameters of the ferro-elastic material: thickness t _ME = 5 nm, dielectric constant ε = 500, area A = 60 nm x 20 nm. Then the capacitance is given as: [0066] Demonstrated values of the magnetoelectric coefficient is a _ME ~10/c , where the speed of light is c. This translates to the effective magnetic field exerted on second magnet 208, which is expressed as:

BME = a _ME E = -0.06Γ

This is a strong field sufficient to switch magnetization.

[0067] The charge on the capacitor Q =— x 10 mV = 10 aC, and the time to fully charge it to the induced voltage is td = 10— ~1 ps (with the account of decreased voltage difference as the capacitor charges). If the driving voltage is V _d = 100 mV, then the energy E _sw to switch is expressed as:

ii _sw ~ 100mV ^, x l00 -4x lps~10a/

which is comparable to the switching energy of CMOS transistors. Note that the time to switch t _sw magnetization remains much longer than the charging time and is determined by the magnetization precession rate. The micro-magnetic simulations predict this time to be t _sw ~100ps, for example.

[0068] In some embodiments, materials for first and second magnets 201 and 208 have saturated magnetization M _s and effective anisotropy field Hk. Saturated magnetization Ms is generally the state reached when an increase in applied external magnetic field H cannot increase the magnetization of the material. Anisotropy Hk generally refers material properties that are highly directionally dependent. In some embodiments, materials for first and second magnets 201 and 208 are non-ferromagnetic elements with strong paramagnetism which have high number of unpaired spins but are not room temperature ferromagnets.

[0069] In some embodiments, the stack of layers comprises: a first layer 202 comprising Ag, wherein the first layer is adjacent to first magnet 201 ; and a second layer 204 comprising Bi or W, wherein second layer 204 is adjacent to first layer 202 and to conductor 205. In some embodiments, a third layer 203 (having material which is one or more of Ta, W, or Pt) is sandwiched between first layer 202 and second layer 204 as shown. In some embodiments, the stack of layers comprises a material which includes one of: β-Ta, β-W, W, Pt, Cu doped with Iridium, Cu doped with Bismuth, or Cu doped an element of 3d, 4d, 5d, 4f, or 5f of periodic table groups. [0070] Fig. 3A illustrates a spin orbit material stack 300 at the input of an

interconnect producing charge current from spins polarized in a first direction, according to some embodiments of the disclosure. Fig. 3B illustrates a spin orbit material stack 320 at the input of the interconnect producing zero charge current from spins polarized in a second direction, according to some embodiments of the disclosure. In stack 300, in-plane magnetization of magnet 201 causes spins to be polarized in-plane in the same direction as the magnetization of magnet 201. The in-plane polarized spins are converted by layers 202, 203 and 204 into charge current I _c which flows orthogonal to the spin polarization. In stack 300, out-of-plane magnetization of magnet 201 causes spins to be polarized out-of-plane in the same direction as the magnetization of magnet 201. The cross-product of spin polarization σ and spin current J _s is zero, which means that no charge current is provided by stack 320. This illustrates the two stable states of MESO logic. In a first state, the magnet may have in-plane magnetization producing charge current, and in a second state, the magnet may have out-of-plane magnetization producing zero charge current. The magnetizations (in- plane or out-of-plane) of the magnets 201/208 are determined by magnetostriction, in accordance with various embodiments.

[0071] Figs. 4A-B illustrate two logic states of MESO logic 400 and 420, respectively, operable as an inverter, according to some embodiments. It is pointed out that those elements of Figs. 4A-B having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. In some embodiments, to configure MESO logic 200 as an inverter, a positive supply (e.g., +Vdd) is applied to transistors MP 1 and MP2. In some embodiments, the clocking signals, Vd and Vd_t>, enable operation of stages of MESO logic 400

consecutively. For example, in one of the clocking stages, magnet 201 is coupled to +Vdd via high conductance in transistor MP 1 while magnet 208 is coupled to ground via high conductance in transistor MN2.

[0072] With reference to Fig. 4A, a zero input charge current Icharge(iN) causes layers

206b and 207b to exert no stress on magnet 201 , and by magnetostrictive effect the magnetization of magnet 201 switches to in-plane magnetization. The in-plane magnetization 401 of magnet 201 causes injection of in-plane polarized spins into layer 202a which is then converted to charge current Ichar _g e(OUT),by the inverse spin Hall effect. This charge current Icharge(OUT) is greater than zero as indicated by reference sign 402. The charge current I _c causes layers 206a and 207a to exert stress on magnet 208, and by magnetostrictive effect the magnetization of magnet 208 switches to out-of-plane magnetization 403, in other words logically inverse to the state of magnet 201. This out-of-plane magnetization 403 produces out-of-plane polarized spins in layer 202b. The out-of-plane polarized spins are then converted by layers 202b, 203b, and 204b into zero charge current I _C harge(2) by spin orbit coupling.

[0073] With reference to Fig. 4B, the positive input charge Icharge(iN) causes layers

206b and 207b to exert stress on magnet 201. The stress in turn causes magnetization of magnet 201 to switch to out-of-plane magnetization as shown by direction 421. The out-of- plane magnetization 421 of magnet 201 in turn causes out-of-plane polarized spins to be received by layer 202a. However, in this case, the charge current is zero because the stack of layers 202a, 203a, and 204a does not convert the out-of-plane polarized spins into charge current. As such, current Icharge (OUT) is zero in conductor 405 as indicated by reference sign 422. The lack of current in conductor 205 causes layers 206a and 207a to exert no stress such that the magnetization of magnet 208 switches to in-plane magnetization as indicated by reference sign 423, in other words logically inverse to the state of magnet 201. This behavior is similar to the dynamics discussed with reference to Figs. 1A-B where hysteresis plots shift. The in-plane magnetization 423 generates in-plane polarized spins for layer 202b. These in- plane polarized spins are converted into charge I _C harge(2) by layers 202b, 203b, and 204b using spin orbit coupling.

[0074] In various embodiments, for repeater MESO logic 400/420, the magnetization direction of first magnet 201 is orthogonal to the magnetization direction of second magnet 208. For example, the magnetization direction of first magnet 201 is in the -y direction 401 while the magnetization direction of second magnet 208 is also in the -z direction 403.

[0075] In some embodiments, a repeater is formed by cascading in series two MESO devices. For example, a MESO device comprising magnet 201 and a MESO device comprising magnet 208 as shown in circuit 400 can be used to form a repeater. There the state of magnet 208 will be the same as the state of a prior stage of a MESO circuit (not shown in the drawing) which produces current Icharge(iN). Alternatively the repeater/buffer action is seen from the fact of equality of current Icharge(iN) and I _C har _g e(2). As such, back-to-back series coupled MESO inverters would produce a MESO repeater behavior, in accordance with some embodiments.

[0076] Fig. 5 illustrates a top view of a layout of the MESO logic, according to some embodiments. An integration scheme for SOL devices with CMOS drivers for power supply and clocking is shown in the top view. Here, transistor MP1 is formed in the active region 501, and power supply is provided via metal layer 3 (M3) indicated as 506. The gate terminal 504 of transistor MP1 is coupled to a supply interconnect 505 through via or contact 503. In some embodiments, M3 layer 507 is coupled to ground which provides ground supply to layer 204. In some embodiments, another transistor can be formed in active region 503 with gate terminal 510. Here, regions 508 and 509 are contact vias coupled to a power supply line. In some embodiments, the density of integration of the devices exceeds that of CMOS since an inverter operation can be achieved within 2.5P x 2M0. In some

embodiments, since the power transistor MP1 can be shared among all the devices at the same clock phases, vertical integration can also be used to increase the logic density as described with reference to Fig. 6, in accordance with some embodiments.

[0077] Fig. 6 illustrates a majority gate using MESO logic devices, according to some embodiments. Fig. 6 illustrates majority gate 600 using magnetoelectric SOL devices, according to some embodiments. It is pointed out that those elements of Fig. 6 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. A charge mediated majority gate is proposed using the spin orbit coupling and magnetostrictive switching. A charge mediated majority gate is shown in Fig. 6. Majority gate 600 comprises at least three input stages 601, 602, and 603 with their respective charge conductors 205i, 2052, and 2053 coupled to summing interconnect 604. In some embodiments, summing interconnect 604 is made of the same materials as interconnect 205. In some embodiments, summing interconnect 604 is coupled to output stage 605 which includes the second magnet 208. The three input stages 601, 602, and 603 share a common power/clock region therefore the power/clock gating transistor can be shared among the three inputs of the majority gate, in accordance with some embodiments. The input stages 601, 602, and 603 can also be stacked vertically to improve the logic density, in accordance with some embodiments. The charge current at the output (I _C har _g e(2)) is the sum of currents I _C hi, Ich2, and I _C h3.

[0078] MESO devices of various embodiments provide logic cascadability and unidirectional signal propagation (e.g., input-output isolation). The unidirectional nature of logic is ensured due to large difference in impedance for injection path versus detection path, in accordance with some embodiments. In some embodiments, the injector is essentially a metallic spin valve with spin to charge transduction with RA (resistance area) products of approximately 10 mOhrarnicron ² . In some embodiments, the detection path is a low leakage capacitance with RA products much larger than 1 MOhm. micron ² in series with the resistance of the magnetic capacitor plate with estimated resistance greater than 500 Ohms. [0079] Fig. 7 illustrates a top view of layout 700 of majority gate 600, according to some embodiments. It is pointed out that those elements of Fig. 7 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. Majority gate 700 comprises at least three input stages 601/701, 602/702, and 603/703 with their respective conductors 205i, 2052, and 2053 coupled to summing interconnect 604/704 and output stage 605/705.

[0080] Fig. 8 illustrates a MESO inverter 800 with a different layout but the same functionality as inverter 200, according to some embodiments. It is pointed out that those elements of Fig. 8 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. MESO logic device 800 is similar to MESO device 200, but with the two magnets in different positions such that conductor 205 (now labeled as 805a/b/c) turns 90 degrees twice to couple magnet 201 with magnet 208, in accordance with some

embodiments. Compared to MESO device 200, conductor 205 is replaced with conductors 805a, 805b, and 805c. Material wise, conductors 805a, 805b, and 805c have the same material as conductor 205. Functionally, MESO logic device 800 operates same as MESO device 400/420.

[0081] Fig. 9 illustrates a MESO repeater/buffer 900 accomplished in just one stage rather than two, according to some embodiments. MESO logic device 900 is similar to MESO device 200, but with the two magnets in different positions such that conductor 905a/b/c) turns 90 degrees twice to couple magnet 201 with magnet 208, in accordance with some embodiments. In some embodiments, for MESO repeater/buffer 900 the set of materials for electrodes in the stack of layers 911, 906b, 907b (and similarly in all stages of the circuit) is reversed compared to inverter 200, and is equivalent to the stack in Fig. IB. In some embodiments, material wise, conductors 911, 905a, 905b, and 905c have the same material as conductor 207b, and conductor 907b is the same as conductor 211a.

[0082] As a result of these changes, in circuit 900 the charge current Icharge(OUT) though having the same geometrical direction in the vicinity of magnet 208 as the current in circuit 800, would have an opposite logic direction - from magnet 208 towards magnet 201. Thus it will produce a charge of the opposite sign on the capacitor formed by layer 906a. Thus the negative charge on the capacitor 906a will lead to in-plane magnetization in magnet 208, in accordance with some embodiments. In some embodiments, a zero charge on the capacitor 906a will lead to out-of-plane magnetization in magnet 208. In other words, the logic states of magnet 201 and magnet 208 will be the same resulting in a buffer or repeater behavior. Also the currents Icharge(iN), Icharge(ouT), and I _C har _g e(2) will have the same logic value, in accordance with some embodiments.

[0083] Fig. 10 illustrates a smart device or a computer system or a SoC (System-on-

Chip) with MESO logic, according to some embodiments. It is pointed out that those elements of Fig. 10 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0084] Fig. 10 illustrates a block diagram of an embodiment of a mobile device in which flat surface interface connectors could be used. In some embodiments, computing device 1600 represents a mobile computing device, such as a computing tablet, a mobile phone or smart-phone, a wireless-enabled e-reader, or other wireless mobile device. It will be understood that certain components are shown generally, and not all components of such a device are shown in computing device 1600.

[0085] In some embodiments, computing device 1600 includes first processor 1610 with MESO logic, according to some embodiments discussed. Other blocks of the computing device 1600 may also include MESO logic, according to some embodiments. The various embodiments of the present disclosure may also comprise a network interface within 1670 such as a wireless interface so that a system embodiment may be incorporated into a wireless device, for example, cell phone or personal digital assistant.

[0086] In some embodiments, processor 1610 can include one or more physical devices, such as microprocessors, application processors, microcontrollers, programmable logic devices, or other processing means. The processing operations performed by processor 1610 include the execution of an operating platform or operating system on which applications and/or device functions are executed. The processing operations include operations related to I/O (input/output) with a human user or with other devices, operations related to power management, and/or operations related to connecting the computing device 1600 to another device. The processing operations may also include operations related to audio I/O and/or display I/O.

[0087] In some embodiments, computing device 1600 includes audio subsystem

1620, which represents hardware (e.g., audio hardware and audio circuits) and software (e.g., drivers, codecs) components associated with providing audio functions to the computing device. Audio functions can include speaker and/or headphone output, as well as microphone input. Devices for such functions can be integrated into computing device 1600, or connected to the computing device 1600. In one embodiment, a user interacts with the computing device 1600 by providing audio commands that are received and processed by processor 1610.

[0088] In some embodiments, computing device 1600 comprises display subsystem

1630. Display subsystem 1630 represents hardware (e.g., display devices) and software (e.g., drivers) components that provide a visual and/or tactile display for a user to interact with the computing device 1600. Display subsystem 1630 includes display interface 1632, which includes the particular screen or hardware device used to provide a display to a user. In one embodiment, display interface 1632 includes logic separate from processor 1610 to perform at least some processing related to the display. In one embodiment, display subsystem 1630 includes a touch screen (or touch pad) device that provides both output and input to a user.

[0089] In some embodiments, computing device 1600 comprises I/O controller 1640.

I/O controller 1640 represents hardware devices and software components related to interaction with a user. I/O controller 1640 is operable to manage hardware that is part of audio subsystem 1620 and/or display subsystem 1630. Additionally, I/O controller 1640 illustrates a connection point for additional devices that connect to computing device 1600 through which a user might interact with the system. For example, devices that can be attached to the computing device 1600 might include microphone devices, speaker or stereo systems, video systems or other display devices, keyboard or keypad devices, or other I/O devices for use with specific applications such as card readers or other devices.

[0090] As mentioned above, I/O controller 1640 can interact with audio subsystem

1620 and/or display subsystem 1630. For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of the computing device 1600. Additionally, audio output can be provided instead of, or in addition to display output. In another example, if display subsystem 1630 includes a touch screen, the display device also acts as an input device, which can be at least partially managed by I/O controller 1640. There can also be additional buttons or switches on the computing device 1600 to provide I/O functions managed by I/O controller 1640.

[0091] In some embodiments, I/O controller 1640 manages devices such as accelerometers, cameras, light sensors or other environmental sensors, or other hardware that can be included in the computing device 1600. The input can be part of direct user interaction, as well as providing environmental input to the system to influence its operations (such as filtering for noise, adjusting displays for brightness detection, applying a flash for a camera, or other features). [0092] In some embodiments, computing device 1600 includes power management

1650 that manages battery power usage, charging of the battery, and features related to power saving operation. Memory subsystem 1660 includes memory devices for storing information in computing device 1600. Memory can include nonvolatile (state does not change if power to the memory device is interrupted) and/or volatile (state is indeterminate if power to the memory device is interrupted) memory devices. Memory subsystem 1660 can store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of the applications and functions of the computing device 1600.

[0093] Elements of embodiments are also provided as a machine-readable medium

(e.g., memory 1660) for storing the computer-executable instructions (e.g., instructions to implement any other processes discussed herein). The machine-readable medium (e.g., memory 1660) may include, but is not limited to, flash memory, optical disks, CD-ROMs, DVD ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, phase change memory (PCM), or other types of machine-readable media suitable for storing electronic or computer- executable instructions. For example, embodiments of the disclosure may be downloaded as a computer program (e.g., BIOS) which may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals via a communication link (e.g., a modem or network connection).

[0094] In some embodiments, computing device 1600 comprises connectivity 1670.

Connectivity 1670 includes hardware devices (e.g., wireless and/or wired connectors and communication hardware) and software components (e.g., drivers, protocol stacks) to enable the computing device 1600 to communicate with external devices. The computing device 1600 could be separate devices, such as other computing devices, wireless access points or base stations, as well as peripherals such as headsets, printers, or other devices.

[0095] Connectivity 1670 can include multiple different types of connectivity. To generalize, the computing device 1600 is illustrated with cellular connectivity 1672 and wireless connectivity 1674. Cellular connectivity 1672 refers generally to cellular network connectivity provided by wireless carriers, such as provided via GSM (global system for mobile communications) or variations or derivatives, CDMA (code division multiple access) or variations or derivatives, TDM (time division multiplexing) or variations or derivatives, or other cellular service standards. Wireless connectivity (or wireless interface) 1674 refers to wireless connectivity that is not cellular, and can include personal area networks (such as Bluetooth, Near Field, etc.), local area networks (such as Wi-Fi), and/or wide area networks (such as WiMax), or other wireless communication.

[0096] In some embodiments, computing device 1600 comprises peripheral connections 1680. Peripheral connections 1680 include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) to make peripheral connections. It will be understood that the computing device 1600 could both be a peripheral device ("to" 1682) to other computing devices, as well as have peripheral devices ("from" 1684) connected to it. The computing device 1600 commonly has a "docking" connector to connect to other computing devices for purposes such as managing (e.g., downloading and/or uploading, changing, synchronizing) content on computing device 1600. Additionally, a docking connector can allow computing device 1600 to connect to certain peripherals that allow the computing device 1600 to control content output, for example, to audiovisual or other systems.

[0097] In addition to a proprietary docking connector or other proprietary connection hardware, the computing device 1600 can make peripheral connections 1680 via common or standards-based connectors. Common types can include a Universal Serial Bus (USB) connector (which can include any of a number of different hardware interfaces), DisplayPort including MiniDisplayPort (MDP), High Definition Multimedia Interface (HDMI), Firewire, or other types.

[0098] Reference in the specification to "an embodiment," "one embodiment," "some embodiments," or "other embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments. The various appearances of "an embodiment," "one embodiment," or "some embodiments" are not necessarily all referring to the same embodiments. If the specification states a component, feature, structure, or characteristic "may," "might," or "could" be included, that particular component, feature, structure, or characteristic is not required to be included. If the specification or claim refers to "a" or "an" element, that does not mean there is only one of the elements. If the specification or claims refer to "an additional" element, that does not preclude there being more than one of the additional element.

[0099] Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment anywhere the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

[00100] While the disclosure has been described in conjunction with specific embodiments thereof, many alternatives, modifications and variations of such embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. The embodiments of the disclosure are intended to embrace all such alternatives, modifications, and variations as to fall within the broad scope of the appended claims.

[00101] In addition, well known power/ground connections to integrated circuit (IC) chips and other components may or may not be shown within the presented figures, for simplicity of illustration and discussion, and so as not to obscure the disclosure. Further, arrangements may be shown in block diagram form in order to avoid obscuring the disclosure, and also in view of the fact that specifics with respect to implementation of such block diagram arrangements are highly dependent upon the platform within which the present disclosure is to be implemented (i.e., such specifics should be well within purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the disclosure, it should be apparent to one skilled in the art that the disclosure can be practiced without, or with variation of, these specific details. The description is thus to be regarded as illustrative instead of limiting.

[00102] The following examples pertain to further embodiments. Specifics in the examples may be used anywhere in one or more embodiments. All optional features of the apparatus described herein may also be implemented with respect to a method or process.

[00103] Example 1 is an apparatus which comprises: a first magnet; a stack of layers, a portion of which is adjacent to the first magnet, wherein the stack of layers is to provide an inverse spin-orbit coupling effect; a second magnet; one or more layers to provide magnetostrictive effect to the second magnet, wherein one of the layers of the one or more layers is adjacent to the second magnet; and a conductor coupled to at least a portion of the stack of layers and the one or more layers.

[00104] Example 2 includes all features of example 1, wherein one or more layers to provide magnetostrictive effect comprises: a first layer to provide piezoelectric effect, the first layer adjacent to the conductor; and a second layer adjacent to the first layer, the second layer comprising conductive oxide and/or conductive nitride material, wherein the second layer is adjacent to the second magnet. [00105] Example 3 is according to any one of examples 1 or 2, wherein the conductor is to carry a unipolar voltage swing signal which swings between zero and a positive value, or zero and a negative value.

[00106] Example 4 is according to example 2, wherein the first layer is to switch between zero volts and a positive value, or zero volts and a negative value.

[00107] Example 5 includes all features of example 2, wherein the first layer comprises a material which includes one of: BFO class of perovskites, tetragonal zirconia, or LCO class of perovskites, lead zirconate titanate Pb[Zr _x Tii- _x ]0 ₃ (PZT), barium titanate BaTiCb (BTO), Pb(ZnxNbi- _x )0 ₃ -PbTi0 ₃ (PZN-PT), BiFeCb (BFO), polyvinylidene difluoride (PVDF), or sodium potassium niobate ((K,Na)Nb0 ₃ ).

[00108] Example 6 includes all features of example 5, wherein the BFO class of perovskites includes one of: Bi, Fe, O, Lu, La, or Ce.

[00109] Example 7 includes all features of example 5, wherein the LCO class of perovskites includes one of: Ba, Sr, Co, Fe, O, or La.

[00110] Example 8 includes all features of example 1, wherein the one or more layers to provide magnetostrictive effect comprises: a first layer adjacent to the conductor, the first layer including Pt; a second layer adjacent to the first layer, the second layer including a piezoelectric material; and a third layer adjacent to the second layer, the third layer comprising SRO material, wherein the third layer is adjacent to the second magnet.

[00111] Example 9 includes all features of example 8, wherein the piezoelectric material includes PMN-PT.

[00112] Example 10 includes all features of example 8, wherein piezoelectric material includes one of lead, magnesium, or niobate-lead titanate.

[00113] Example 11 includes all features of example 1, wherein the first and second magnets are paramagnets which include one or more of: Pt, Pd, W, Ce, Al, Li, Mg, Na, Cr ₂ 0 ₃ , CoO, Dy, Dy ₂ 0, Er, Er ₂ 0 ₃ , Eu, Eu ₂ 0 ₃ , Gd, Gd ₂ 0 ₃ , FeO, Fe ₂ 0 ₃ , Nd, Nd ₂ 0 ₃ , K0 ₂ , Pr, Sm, SrmOs, Tb, Tb ₂ 0 ₃ , Tm, Tm ₂ 0 ₃ , V, or V ₂ 0 ₃ .

[00114] Example 12 is according to any one of examples 1 to 11, wherein the stack of layers comprises: a first layer comprising Ag, wherein the first layer is adjacent to the first magnet; and a second layer comprising Bi or W, wherein the second layer is adjacent to the first layer and to the conductor.

[00115] Example 13 is according to any of the preceding examples, wherein the conductor comprises a material which includes one or more of: Cu, Ag, Al, or Au. [00116] Example 14 is according to any of the preceding claims, wherein the stack of layers comprises a material which comprises one or more of: β-Ta, β-W, W, Pt, Cu doped with Iridium, Cu doped with Bismuth, or Cu doped an element of 3d, 4d, 5d, 4f, or 5f of periodic table groups.

[00117] Example 15 includes all features of example 1, and comprises a transistor coupled to the first magnet.

[00118] Example 16 includes all features of example 1, wherein a portion of the stack of the layers is coupled to ground, wherein the first magnet is coupled to a positive supply, and wherein the second magnet is coupled to ground.

[00119] Example 17 includes all features of example 1, wherein the first and second magnets are ferromagnets which comprise one of Heusler alloy, Co, Fe, Ni, Gd, B, Ge, Ga, or a combination of them, and wherein the Heusler alloys include one of: Cu ₂ MnAl, Cu ₂ MnIn, Cu ₂ MnSn, Ni ₂ MnAl, Ni ₂ MnIn, Ni ₂ MnSn, Ni ₂ MnSb, Ni ₂ MnGa Co ₂ MnAl, Co ₂ MnSi,

Co ₂ MnGa, CoJVInGe, Pd ₂ MnAl, PdJVInln, Pd ₂ MnSn, Pd ₂ MnSb, Co ₂ FeSi, Co ₂ FeAl, Fe ₂ VAl, Mn ₂ VGa, Co ₂ FeGe, MnGa, or MnGaRu.

[00120] Example 18 is an apparatus which comprises: a magnet having a first portion and a second portion; a stack of layers one of which is adjacent to the first portion of the magnet, wherein the stack of layers is to provide an inverse spin orbit coupling effect; one or more layers to provide magnetostrictive effect to the magnet, wherein one layer of the one or more layers is adjacent to the magnet; and a conductor adjacent to one of the one or more layers.

[00121] Example 19 includes all features of example 18, wherein the magnet is a ferromagnet which comprise one of Heusler alloy, Co, Fe, Ni, Gd, B, Ge, Ga, or a combination of them, and wherein the Heusler alloys include one of: Cu ₂ MnAl, Cu ₂ MnIn, Cu ₂ MnSn, Ni ₂ MnAl, Ni ₂ MnIn, Ni ₂ MnSn, Ni ₂ MnSb, Ni ₂ MnGa Co ₂ MnAl, Co ₂ MnSi,

Co ₂ MnGa, CoJVInGe, Pd ₂ MnAl, PdJVInln, Pd ₂ MnSn, Pd ₂ MnSb, Co ₂ FeSi, Co ₂ FeAl, Fe ₂ VAl, Mn ₂ VGa, Co ₂ FeGe, MnGa, or MnGaRu.

[00122] Example 20 includes all features of example 19, wherein the one or more layers comprise a material which includes one of: lead Zirconate Titanate, BFO class of perovskites, tetragonal zirconia, or LCO class of perovskites.

[00123] Example 21 includes all features of example 20, wherein the BFO class of perovskites includes one of: Bi, Fe, O, Lu, La, or Ce.

[00124] Example 22 includes all features of example 20, wherein the LCO class of perovskites includes one of: Ba, Sr, Co, Fe, O, or La. [00125] Example 23 includes all features of example 20, wherein the one or more layers to provide magnetostrictive effect comprises: a first layer including Pt; a second layer adjacent to the first layer, the second layer including a piezoelectric material; and a third layer adjacent to the second layer, the third layer comprising SRO material.

[00126] Example 24 includes all features of example 23, wherein the piezoelectric material includes PMN-PT.

[00127] Example 25 is according to any of examples 18 to 23, wherein the stack of layers comprises a material which includes one or more of: β-Ta, β-W, W, Pt, Cu doped with Iridium, Cu doped with Bismuth, or Cu doped an element of 3d, 4d, 5d, 4f, or 5f of periodic table groups.

[00128] Example 26 is according to any of examples 18 to 23, wherein the magnet is a paramagnet, and wherein the paramagnets comprise a material which includes one or more of: Pt, Pd, W, Ce, Al, Li, Mg, Na, Cr ₂ 0 ₃ , CoO, Dy, Dy ₂ 0, Er, Er ₂ 0 ₃ , Eu, Eu ₂ 0 ₃ , Gd, Gd ₂ 0 ₃ , FeO, Fe ₂ 0 ₃ , Nd, Nd ₂ 0 ₃ , K0 ₂ , Pr, Sm, Sm ₂ 0 ₃ , Tb, Tb ₂ 0 ₃ , Tm, Tm ₂ 0 ₃ , V, or V ₂ 0 ₃ .

[00129] Example 27 is a system comprising: a memory; a processor coupled to the memory, the processor including an apparatus according to any one of apparatus examples 1 to 17 or apparatus examples 18 to 26; and a wireless interface to allow the processor to communicate with another device.

[00130] Example 28 is a method which comprises: forming a first magnet; forming a stack of layers, a portion of which is adjacent to the first magnet, wherein the stack of layers is to provide an inverse spin-orbit coupling effect; forming a second magnet; forming one or more layers to provide magnetostrictive effect to the second magnet, wherein one of the layers of the one or more layers is adjacent to the second magnet; and forming a conductor coupled to at least a portion of the stack of layers and the one or more layers.

[00131] Example 29 includes all features of example 28, wherein forming one or more layers to provide magnetostrictive effect comprises: forming a first layer to provide piezoelectric effect, the first layer adjacent to the conductor; and forming a second layer adjacent to the first layer, the second layer comprising conductive oxide and/or conductive nitride material, wherein the second layer is adjacent to the second magnet.

[00132] Example 30 is according to any one of examples 28 or 29, carrying a unipolar voltage swing signal which swings between zero and a positive value, or zero and a negative value.

[00133] Example 31 is according to example 29 comprises switching between zero volts and a positive value, or zero volts and a negative value. [00134] Example 32 includes all features of example 29, wherein the first layer comprises a material which includes one of: BFO class of perovskites, tetragonal zirconia, or LCO class of perovskites, lead zirconate titanate Pb[Zr _x Tii- _x ]0 ₃ (PZT), barium titanate BaTiCb (BTO), Pb(Zn _x Nbi- _x )0 ₃ -PbTi0 ₃ (PZN-PT), BiFe0 ₃ (BFO), polyvinylidene difluoride (PVDF), or sodium potassium niobate ((K,Na)Nb0 ₃ ).

[00135] Example 33 includes all features of example 32, wherein the BFO class of perovskites includes one of: Bi, Fe, O, Lu, La, or Ce.

[00136] Example 34 includes all features of example 32, wherein the LCO class of perovskites includes one of: Ba, Sr, Co, Fe, O, or La.

[00137] Example 35 includes all features of example 28, wherein the forming one or more layers to provide magnetostrictive effect comprises: forming a first layer adjacent to the conductor, the first layer including Pt; forming a second layer adjacent to the first layer, the second layer including a piezoelectric material; and forming a third layer adjacent to the second layer, the third layer comprising SRO material, wherein the third layer is adjacent to the second magnet.

[00138] Example 36 includes all features of example 35, wherein the piezoelectric material includes PMN-PT.

[00139] Example 37 includes all features of example 36, wherein piezoelectric material includes one of lead, magnesium, or niobate-lead titanate.

[00140] Example 38 includes all features of example 28, wherein the first and second magnets are paramagnets which include one or more of: Pt, Pd, W, Ce, Al, Li, Mg, Na, Cr ₂ 0 ₃ , CoO, Dy, Dy ₂ 0, Er, Er ₂ 0 ₃ , Eu, Eu ₂ 0 ₃ , Gd, Gd ₂ 0 ₃ , FeO, Fe ₂ 0 ₃ , Nd, Nd ₂ 0 ₃ , K0 ₂ , Pr, Sm, SrmOs, Tb, Tb ₂ 0 ₃ , Tm, Tm ₂ 0 ₃ , V, or V ₂ 0 ₃ .

[00141] Example 39 is according to any one of examples 28 to 38, wherein forming the stack of layers comprises: forming a first layer comprising Ag, wherein the first layer is adjacent to the first magnet; and forming a second layer comprising Bi or W, wherein the second layer is adjacent to the first layer and to the conductor.

[00142] Example 40 is according to any one of claims 28 to 39, wherein the conductor comprises a material which includes one or more of: Cu, Ag, Al, or Au.

[00143] Example 41 is according to any one of claims 28 to 39, wherein the stack of layers comprises a material which comprises one or more of: β-Ta, β-W, W, Pt, Cu doped with Iridium, Cu doped with Bismuth, or Cu doped an element of 3d, 4d, 5d, 4f, or 5f of periodic table groups. [00144] Example 42 includes all features of example 28, and comprises forming a transistor coupled to the first magnet.

[00145] Example 43 includes all features of example 28, and comprises: coupling a portion of the stack of the layers to ground, coupling the first magnet to a positive supply, and coupling the second magnet to ground.

[00146] Example 44 includes all features of example of 28, wherein the first and second magnets are ferromagnets which comprise one of Heusler alloy, Co, Fe, Ni, Gd, B, Ge, Ga, or a combination of them, and wherein the Heusler alloys include one of: Cu ₂ MnAl, Cu ₂ MnIn, Cu ₂ MnSn, Ni ₂ MnAl, Ni ₂ MnIn, Ni ₂ MnSn, Ni ₂ MnSb, Ni ₂ MnGa Co ₂ MnAl,

Co ₂ MnSi, Co ₂ MnGa, CoJVInGe, Pd ₂ MnAl, Pd ₂ MnIn, PdJVInSn, PdJVInSb, Co ₂ FeSi, Co ₂ FeAl, Fe ₂ VAl, Mn ₂ VGa, Co ₂ FeGe, MnGa, or MnGaRu.

[00147] Example 45 is a method which comprises: forming a magnet having a first portion and a second portion; forming a stack of layers one of which is adjacent to the first portion of the magnet, wherein the stack of layers is to provide an inverse spin orbit coupling effect; forming one or more layers to provide magnetostrictive effect to the magnet, wherein one layer of the one or more layers is adjacent to the magnet; and forming a conductor adjacent to one of the one or more layers.

[00148] Example 46 includes all features of example 45, wherein the magnet is a ferromagnet which comprise one of Heusler alloy, Co, Fe, Ni, Gd, B, Ge, Ga, or a combination of them, and wherein the Heusler alloys include one of: Cu ₂ MnAl, Cu ₂ MnIn, Cu ₂ MnSn, Ni ₂ MnAl, Ni ₂ MnIn, Ni ₂ MnSn, Ni ₂ MnSb, Ni ₂ MnGa Co ₂ MnAl, Co ₂ MnSi,

Co ₂ MnGa, CoJVInGe, Pd ₂ MnAl, PdJVInln, Pd ₂ MnSn, Pd ₂ MnSb, Co ₂ FeSi, Co ₂ FeAl, Fe ₂ VAl, Mn ₂ VGa, Co ₂ FeGe, MnGa, or MnGaRu.

[00149] Example 47 includes all features of example 45, wherein the one or more layers comprise a material which includes one of: lead Zirconate Titanate, BFO class of perovskites, tetragonal zirconia, or LCO class of perovskites.

[00150] Example 48 includes all features of example 45, wherein the BFO class of perovskites includes one of: Bi, Fe, O, Lu, La, or Ce.

[00151] Example 49 includes all features of example 45, wherein the LCO class of perovskites includes one of: Ba, Sr, Co, Fe, O, or La.

[00152] Example 50 includes all features of example 45, wherein forming the one or more layers to provide magnetostrictive effect comprises: forming a first layer including Pt; forming a second layer adjacent to the first layer, the second layer including a piezoelectric material; and forming a third layer adjacent to the second layer, the third layer comprising SRO material.

[00153] Example 51 includes all features of example 50, wherein the piezoelectric material includes PMN-PT.

[00154] Example 52 is according to any of examples 45 to 51, wherein the stack of layers comprises a material which includes one or more of: β-Ta, β-W, W, Pt, Cu doped with Iridium, Cu doped with Bismuth, or Cu doped an element of 3d, 4d, 5d, 4f, or 5f of periodic table groups.

[00155] Example 53 is according to any of claims 45 to 51, wherein the magnet is a paramagnet, and wherein the paramagnets comprise a material which includes one or more of: Pt, Pd, W, Ce, Al, Li, Mg, Na, Cr ₂ 0 ₃ , CoO, Dy, Dy ₂ 0, Er, Er ₂ 0 ₃ , Eu, Eu ₂ 0 ₃ , Gd, Gd ₂ 0 ₃ , FeO, Fe ₂ 0 ₃ , Nd, Nd ₂ 0 ₃ , K0 ₂ , Pr, Sm, Sm ₂ 0 ₃ , Tb, Tb ₂ 0 ₃ , Tm, Tm ₂ 0 ₃ , V, or V ₂ 0 ₃ .

[00156] An abstract is provided that will allow the reader to ascertain the nature and gist of the technical disclosure. The abstract is submitted with the understanding that it will not be used to limit the scope or meaning of the claims. The following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.