Manufacture of CdTe Photovoltaic Cells Using MOCVD

The present invention relates to the manufacture of photovoltaic cells and in particular to the manufacture of CdTe based (cadmium telluride) photovoltaic cells by metal organic chemical vapour deposition (MOCVD).

One form of photovoltaic cell comprises a p-n junction having a radiation absorbing layer which generates electron hole pairs in response to incoming radiation. One suitable material for providing such an absorbing layer is p-type CdTe, which is typically paired with n-type CdS (cadmium sulphide) to form a p-n junction. CdTe is a relatively inexpensive raw material but there are some difficulties in implementing large scale production of reliable CdTe based photovoltaic cells at reasonable cost due to problems with scaling up production processes.

A typical CdTe photovoltaic cell comprises an n-type CdS window layer and a p-type CdTe absorber layer. Often a CdCl ₂ cap layer is also provided to activate the device. The CdS layer is typically grown by chemical bath deposition (CBD) at a temperature lower than 100 ⁰ C. To be thermally stable and improve its quality, the

CdS is then annealed in excess of 400 ⁰ C, possibly in the presence of CdCl ₂ .

The CdTe layer is then generally grown by closed-space sublimation (CSS)

(described in Aramoto, T., Adurodija, F., Nishiyama, Y., Arita, T., Hanafusa, A.,

Omura, K., Morita, A., Solar Energy Materials & Solar Cells, 75 (2003) 211-217 and Ferekides, C. S., Marinskiy, D., Viswanathan, V., Tetali, B., Palekis V., Selvaraj, P.,

& Morel, D. L., Thin Solid Films, 361-362 (2000) 520-526) where the target material

and substrate temperatures are generally in excess of 500 ⁰ C. In some methods the layer is grown at atmospheric pressure but generally it is grown under reduced pressure. CSS is a fast technique but at these temperatures, CdS-CdTe intermixing is inevitable and not easy to control. Also, controlled in situ doping of the CdTe is extremely difficult due to self compensation.

The CdCl ₂ layer may be deposited on the CdTe by spraying an aqueous solution (described in Aramoto, T., Adurodija, F., Nishiyama, Y., Arita, T., Hanafusa, A., Omura, K., Morita, A., Solar Energy Materials & Solar Cells, 75 (2003) 211-217), physical vapour deposition. After the CdCl ₂ layer is deposited annealing is carried out at 400 ⁰ C or more. Alternatively, vapour transport of Chlorine or cadmium chloride during annealing may be used to deposit the CdCl ₂ layer (described in McCandless, B. E., Dobson, K. D., Solar Energy, 77 (2004) 839-856 and Ferekides, C. S., Basasubramanian, U., Mamazza, R., Viswanathan, V., Zhao, H., & Morel, D. L., Solar Energy, 77 (2004) 823-830). In each of these steps, the relatively high process temperatures required provide a relatively high energy cost in manufacturing a cell and hence increase the production costs.

In addition to the drawbacks discussed above, there are other drawbacks with such a production process. For instance, as all the above process steps are different from each other, the device is exposed to external contamination from ambient air while being transferred from one process to the next. This may induce variations in device characteristics as discussed in Emziane, M., Durose, K., Bosio, A., Romeo, N., Halliday, D. P., Journal of Materials Science, 40 (2005) 1-5. Furthermore, as there

are large differences in temperature between successive processes time is lost whilst progressively cooling and heating the substrate to avoid cracking. At any stage, residual stress can be present in the layers depending on their physical properties, annealing time, moisture levels in air and temperature ramping. These residual stresses and/or bad bonding to the substrate can cause delamination of the layers resulting in an unusable product. Additionally, variations of yield can occur due to variations in the purity of the raw materials used as discussed in Emziane, M., Durose, K., Bosio, A., Romeo, N., Halliday, D. P., Journal of Materials Science, 40 (2005) 1- 5.

It is therefore an object of the present invention to provide a method of manufacturing a cell that overcomes or alleviates at least some of the above problems.

According to a first aspect of the present invention there is provided a method of manufacturing a CdTe photovoltaic cell comprising the steps of: growing an n-type

CdS window layer; and growing a p-type CdTe absorber layer characterised in that each of the layers is grown by metal organic chemical vapour deposition (MOCVD) in situ.

By using the above method, a CdTe photovoltaic cell may be grown using a reduced number of processing steps hence reducing cost and complexity.

Additionally, as each of the steps is carried out in situ, contamination as a result of air transfer can be reduced. Additionally, the production yield of cells can be improved as MOCVD is a highly reproducible and tunable process. It is further possible, in

certain embodiments of the method given the tunability of MOCVD, to save energy cost by reducing the deposition and processing temperatures, growing the layers at atmospheric pressure and using less raw materials (i.e. thinner layers).

The above method may be applied to any CdTe based photovoltaic cells containing at least a p-n junction in the form of CdS/CdTe.

Preferably, the method includes the additional step of growing a CdCl ₂ cap layer. The cap layer is preferably grown by MOCVD in situ.

The method may include either or both the further steps of: annealing the cell in situ; and cooling the cell in situ. The cell may be formed on a suitable substrate or superstrate material. In the description below, references to substrate should be understood to also encompass references to superstrate and vice versa, except where details of specific substrate or superstrate embodiments are concerned. With regard to superstrate configuration, suitable materials include, but are not limited to: aluminosilicate (or soda lime) glass or polymer substrates (that may contain a TCO (transparent conductive oxide) layer) or any other transparent conductive medium, rigid or flexible, suitable for superstrate configuration cells. With regard to substrate configuration such materials are also suitable if preferably provided with a patterned contact layer. The superstrate or substrate is preferably cleaned before the layers are grown.

The method may be carried out in a reduced pressure or atmospheric pressure

MOCVD reactor. The MOCVD reactor may be a horizontal MOCVD reactor or a

vertical MOCVD reactor. The precursors used may be alkyls or other volatile chemicals which can crack bond either by pyrolysis, photocatalysis, microwave, plasma, other means or a combination of the above. The carrier gas may be Hydrogen (H ₂ ), Nitrogen (N ₂ ) or other inert gas, reactive gas or mixture of gases. The carrier gas and precursors may be delivered by means of stream diffusers or spray showerheads.

The heat source in the MOCVD reactor may be a resistive heat source such as a graphite element, ceramic element, or other element. Alternatively, the heat source in the MOCVD reactor may be radiation emission using a halogen, infrared, microwave or plasma source as convenient or appropriate.

The thickness and growth characteristics of the layers during MOCVD may be monitored using a triple wavelength interferometer (e.g., wavelengths: 532nm, 635nm & 980nm).

The CdS window layer may be grown from Dimethylcadmium (DMCd) and Ditertiarybutylsulfide (DtBS) organo-metallic precursors. The layer may be grown under a Hydrogen (H ₂ ) atmosphere. The layer may be grown at a substrate temperature in the range 240 to 410 ⁰ C, preferably 250 to 400 ⁰ C and most preferably about 315 ⁰ C. Preferably, the ILVI precursor ratio of the layer is around 1. The total gas flow in the reactor may be in the range 1000 to 10000 seem and is preferably around 3355 seem. The DMCd partial pressure may be in the range IxIO ^"5 to IxIO ^"2 atm, preferably IxIO ^"4 to IxIO ^"3 atm. and most preferably around 2.7 x 10 ^"4 atm. The

layer thickness may be in the range 0.02 to 0.3 μm and preferably around 0.24 μm. In such embodiments, the layer can be grown at a growth rate of 0.12 - 0.14 nm/s, to produce a layer of around 240nm thick and a band gap energy (Eg) of around 2.53eV. If alloyed, to tune its band gap energy, the layer may be grown from Dimethylcadmium (DMCd), Diethylzinc (DEZn) (or Dimethylzinc (DMZn)) and Ditertiarybutylsulfide (DtBS) organo-metallic precursors.

The CdS window layer may also be in situ doped with chlorine or similar dopants, using precursors such as Tertiarybutylchloride (tBuCl), to enhance n-type conversion, promoting electron conduction, and increase its majority carrier concentration. The chlorine doping may be carried out using a double dilution line.

The CdTe absorber layer may be doped with arsenic. The doping may be either even throughout the layer or graded over the layer or concentrated at particular places along the structure. The arsenic doping promotes hole conduction in the CdTe layer, thus making it p-type to form a junction with the n-type CdS. Excess arsenic dopant may segregate to form arsenic tellurides. The arsenic tellurides will typically have their highest concentration at the layer boundary and/or grain boundaries within the absorber layer. This is beneficial because arsenic tellurides are p-type and have low energy band gap which may improve the absorber photo-response and provide an ohmic-like back contact to the junction, which can be difficult to establish with the CdTe layers. The CdTe absorber layer may be grown from Dimethylcadmium (DMCd) and Diisopropyltelluride (DiPTe) organo-metallic precursors. If alloyed, the layer may be grown from Dimethylcadmium (DMCd), Diethylzinc (DEZn) (or

Dimethylzinc (DMZn), Diisopropyltelluride (DiPTe) organo-metallic precursors. If in situ doped, the doping in the layer can done using Tris(Dimethylamino)Arsine (tDMAAs) organo-metallic precursor. The layer may be grown under hydrogen (H ₂ ) atmosphere. The substrate temperature may be in the range 280 to 460 ⁰ C, preferably 300 to 450 ⁰ C and most preferably at around 39O ⁰ C. The total gas flow in the reactor may be in the range 1000 to 10000 seem and preferably is around 4400 seem. The Cd partial pressure may be in the range IxIO ^"2 to 1x10 ^"5 arm., preferably IxIO ^"4 to 1x10 ^" atm. and most preferably around 2 X lO ^"4 arm. The arsenic doping may be carried out using a double dilution line. The partial pressure of As may be in the range 1 x 10 ^"1 to IxIO ^"4 arm., preferably IxIO ^"9 to IxIO ^"5 atm. and most preferably around 1.5 x 10 ^"6 atm. Preferably, there is a substantially uniform concentration of arsenic throughout the cadmium Telluride layer. The concentration of arsenic may be in the range 1 x 1O ⁺¹⁷ to 2 x 1O ⁺¹⁹ atoms.cm ^'3 and is preferably around 2 x 1O ⁺¹⁸ atoms.cm ^"3 . The layer thickness may be in the range 0.6 to 5 μm and preferably around 4 to 5 μm. In such embodiments, the layer can be grown at a growth rate of 0.4 to 0.44 nm/s to produce a layer of 4 to 5 μm thickness with a band gap energy of around 1.53 eV. Preferably, the II: VI precursor ratio of the layer is around 1.82.

The CdCl ₂ cap layer may be grown from Dimethylcadmium (DMCd) and

Teriarybutylchloride (tBuCl) (or n-hexylchloride (nHexCl)) organo-metallic precursors. The layer may be grown at a substrate temperature in the range 100 to

46O ⁰ C, preferably 150 to 400 ⁰ C, and most preferably at around 300 ⁰ C. The layer may be grown under a hydrogen (H ₂ ) atmosphere. The total gas flow in the reactor may be

in the range 1000 to 10000 seem and preferably is around 3500 seem. The Cd partial pressure may be in the range IxIO ^"5 to IxIO ^"2 atm., preferably in the range IxIO^ to 1x10 ^"3 atm. and most preferably around 2.8 x 10 ^"4 atm. The layer thickness may be in the range 0.05 to 1 μm and preferably around 0.45μm. In such embodiments, the layer can be grown at a growth rate of around 5.05 nm/s to produce a layer of around 450 nm thickness. Preferably, the ILVII precursor ratio of the layer is around 0.29.

The annealing process may involve the steps of maintaining the device at a temperature in the range 240 to 52O ⁰ C and preferably around 400 ⁰ C. It may take place for a time period in the range 5 minutes to 1 hour. Preferably, the process may include around 10 minutes under hydrogen. Advantageously, this may take place after a stabilisation period in the range 1 to 10 minutes and preferably of around 5 minutes. The annealing may alternatively take place under any other suitable inert gas (such as argon, nitrogen or helium) and/or reactive gas (such as oxygen or chlorine). The annealing process allows Chlorine (from the CdCl ₂ cap layer) to diffuse through the grain boundaries. This allows the modification/passivation of the grain boundaries thus improving the transport of carriers through the grains and reducing the recombination of charges at the boundaries.

In an alternative embodiment, cap layer formation and annealing can be performed simultaneously. In such a process, the cap layer is grown by use of an alkyl Chloride precursor such as n-hexylchloride (nHexCl), tertiarybutylchloride

(tBuCl) or similar. This can take place at a temperature in the range 240 to 52O ⁰ C and preferably around 400 ⁰ C. The total gas flow in the reactor may be in the range

1000 to 10000 seem and preferably is around 4000 seem. It may take place for a time period in the range 5 minutes to 1 hour. The precursor partial pressure may be in the range lxl0 ^"10 to IxIO ^"3 atm.

Preferably, subsequent to annealing, the device may be cooled to room temperature under hydrogen. Once the device has been cooled, it may be exposed to ambient air for metallisation and measurement of photo-electric characteristics.

In some embodiments, additional steps may be carried out before measurement of photo-electric characteristics. The additional steps may include: slicing the manufactured cell into a plurality of individual devices; etching or scribing two sides of the individual sliced devices to reveal the TCO (e.g., indium tin oxide (ITO)) front contacts; etching the surface of the CdTe layer; depositing material onto the device to create rear contacts.

The etching to reveal the ITO contacts may be carried out using a bromine methanol (BrMeOH) solution. Alternatively, etching can be carried out by the use of a pressurised water spray or other physical or chemical etching process. The etching may take place at any suitable temperature but preferably takes place at a temperature in the range between room temperature to 100 ⁰ C.

Preferably the BrMeOH solution is a 2% Bromine solution. The etching may be carried out with the device area masked by any suitable material. In some embodiments, the masking material comprises adhesive tape.

The etching of the CdTe layer may be carried out using a 0.26% Bromine solution. Preferably, this solution is applied for around 5 seconds so as to remove around 1 μm of the CdTe Layer.

Preferably, the rear contacts comprise a metallic material deposited on the cap layer or an etched region of the cap layer. The contact may have a thickness in the range 0.005 to 1 μm. The material deposited to create the rear contacts may be Gold,

Molybdenum, Nickel or other suitable metal or an alloy or mixture of one or more suitable metals. The contact material may be evaporated from a wire formed from said material. This may be achieved using a tungsten coil. Preferably, this is achieved at a vacuum of around 2 x 10 ^"5 Torr. This may take place a temperature in the range room temperature to 100 ⁰ C.

The above process may also be applied to allow additional substrate and superstrate structures to be grown on a cell.

In one example, MOCVD may be used to grow a layer of transparent conductive oxide (TCO) on the cell. This can improve the conductivity of the front contact while keeping the TCO layer as thin as possible. An example of a suitable

TCO is Cadmium Stannate, further properties of which are described in Mamazza, R.

Jr., Morel, D. L., Ferekides, C. S., Thin Solid Films, 484 (2005) 26-33.

In an optional embodiment, MOCVD can be used to grow a multilayer graded band gap between the window layer and the absorber layer. This can improve charge carrier collection and improve the open-circuit voltage (V _oc ) by optimising the

absorption of photons and increasing the electric field created in the device. The multilayer graded band gap may comprise CdSe.

The CdSe multilayer may be grown from Dimethylcadmium (DMCd) and

Dimethylselenide (DMSe) organo-metallic precursors. The layer may be grown at a substrate temperature in the range 240 to 41O ⁰ C, preferably 320 to 400 ⁰ C, and most preferably at around 35O ⁰ C. The layer may be grown under a hydrogen (H ₂ ) atmosphere. The total gas flow in the reactor may be in the range 1000 to 10000 seem and preferably is around 4000 seem. The Cd partial pressure may be in the range

IxIO ^"2 to IxIO ^"5 atm., preferably IxIO ^"4 to 1x10 ^" atm. and most preferably around 2 x lO^ atm. The layer thickness may be in the range 0.02 to 2 μm.

Additionally or alternatively, MOCVD may be used to grow a high resistivity (high-p) layer on the cell. The growth of such a layer can help to avoid shunting effects, thus resulting in higher open-circuit voltage (V _oc ) and fill factor (FF). Examples of suitable materials for such a high resistivity (high-p) layer include Zinc Stannate, ZnO or ZnS, properties of which are disclosed in Ferekides, C. S., Mamazza, R., Balasubramanian, U., Morel, D. L., Thin Solid Films, 480-481 (2005) 224-229 and Tablero, C, Solar Energy Materials & Solar Cells, 90 (2006) 588-596.

The high resistivity (high-p) layer may be grown from Diethylzinc (DEZn) and Tertiarybutanol (tBuOH) organo-metallic and oxygen precursors respectively. The layer may be grown at a substrate temperature in the range 100 to 400 ⁰ C, preferably 260 to 360 ⁰ C, and most preferably at around 280 ⁰ C. The layer may be

grown under a nitrogen (N ₂ ) atmosphere. The total gas flow in the reactor may be in the range 1000 to 10000 seem and preferably is around 4000 seem. The DEZn partial pressure may be in the range 1x10 ^"4 to 1x10 ^"3 atm., preferably in the range 2x10^ to όxlO ^"4 atm. and most preferably around 4x10^ atm. The layer thickness may be in the range 0.02 to 0.2 μm and preferably around 0.06 μm.

Additionally or alternatively, MOCVD may be used to grow an additional highly p+ doped layer at the back of the cell. This provides the advantage that the back contact has a lower resistance. Examples of suitable p+ material include ZnTe:As or ZnTe:N, properties of which are disclosed in Tablero, C, Solar Energy Materials & Solar Cells, 90 (2006) 588-596 and Spath, B., Thin Solid Films, 480-481 (2005) 204-207. Other suitable materials would include binary/tertiary alloys based upon Cd(Zn)Te. Such alloys may be doped with As or other group V or p-type donor to increase acceptor concentration.

A doped alloy Cd(Zn)Te absorber layer may be grown from Dimethylcadmium (DMCd), Diethylzinc (DEZn) (or Dimethylzinc (DMZn)),

Diisopropyltelluride (DiPTe) and Tris(Dimethylamino)Arsine (tDMAAs) organo- metallic precursors. The layer may be grown under hydrogen (H ₂ ) atmosphere. The substrate temperature may be in the range 280 to 460 ⁰ C, preferably 350 to 420 ⁰ C and most preferably at around 39O ⁰ C. The total gas flow in the reactor may be in the range 1000 to 10000 seem and preferably is around 4500 seem. The Cd partial pressure may be in the range IxIO ^"5 to 1x10 ^"2 arm., preferably IxIO ^"4 to 1x10 ^"3 atm. and most preferably around 2 x 10 ^"4 atm. The arsenic doping may be carried out

using a double dilution line. The partial pressure of As may be in the range 1 x 10 ^"10 to IxIO ^"4 atm, preferably 1x10 ^"7 to 8xlO ^"6 atm. and most preferably around 1.5xlO ^"6 atm. The concentration of arsenic may be in the range 1 x 1O ⁺¹⁷ to 5 x 1O ⁺¹⁹ atoms.cm ^"3 and is preferably around 1.5 x 10 ⁺¹ atoms.cm ^" . The layer thickness may be in the range 0.05 to 1.5 μm and preferably around 0.25 μm.

Additionally or alternatively, MOCVD may be used to grow a layer of heavily As-doped CdTe:As ⁺ . The heavily As-doped CdTe:As ⁺ may increase the electric field and the saturation current of the cell. At a suitable arsenic doping concentration range of IxIO ⁺¹⁸ to 5xlO ⁺¹⁹ atoms.cm ^"3 , and thickness range of 0.05 to 0.5 μm, this layer may enable tunnelling of the carriers, and thus can provide highly p+ doped layer and lower contact series resistance. Also such a heavily As-doped layer may increase further the potential for formation of segregated arsenic tellurides in the grain boundaries.

In an optional embodiment, MOCVD can be used to grow layer of low band gap material between the absorber layer and the cap layer or between the highly p+ doped layer and the cap layer in embodiments with a highly p+ doped layer. The low band gap layer provides the advantage of a wider selection of metal back contact can be used compared to contacting directly to the CdTe layer. The low band gap layer may be formed from As ₂ Te ₃ , Sb ₂ Te ₃ or similar materials.

The low band gap layer may be grown from tris(dimethylamino)arsine

(tDMAAs) and Diisopropyltelluride (DiPTe) organo-metallic precursors in the case of

an As ₂ Te ₃ layer. Alternatively the low band gap layer may be grown from trismethylantimony (tMSb) and Diisopropyltelluride (DiPTe) organo-metallic precursors in the case of an Sb ₂ Te ₃ . The layer may be grown at a substrate temperature in the range 280 to 46O ⁰ C, preferably 320 to 400 ⁰ C, and most preferably at around 39O ⁰ C. The layer may be grown under a hydrogen (H ₂ ) atmosphere. The total gas flow in the reactor may be in the range 1000 to 10000 seem and preferably is around 4400 seem. The As or Sb partial pressure may be in the range IxIO ^"10 to 1x10 ^{" 2} atm., preferably in the range IxIO ^"7 to 1x10 atm. and most preferably around 5x10 ^"

⁵ atm. The layer thickness may be in the range 0.02 to 1 μm and preferably around 0.1 μm.

The method may also include the step of plasma surface etching (as described in Ferekides, C. S., Basasubramanian, U., Mamazza, R., Viswanathan, V., Zhao, H.,

6 Morel, D. L., Solar Energy, 77 (2004) 823-830) to be used to remove potential oxides forming during manufacture of the cell and thus avoid a wet etch. Advantageously, plasma cleaning of the reactor and baking of the susceptor may be carried out in situ without human operator intervention, thus avoiding potential contamination.

Furthermore, the technique can be used to lower the thickness of the CdS layer while avoiding shunting of the CdTe layer to the TCO and hence improve the blue response of the cell.

Additionally, the method may involve controlled variation of the absorber layer doping to increase the p-type carrier concentration of the CdTe. This may be achieved by doping with arsenic as above or by alloying using zinc. Alloying of CdTe using zinc is disclosed in Ferekides, C. S., Mamazza, R., Balasubramanian, U., Morel, D. L., Thin Solid Films, 480-481 (2005) 471-476. The controlled doping may vary defect levels in the material and may lead to beneficial properties of the cells overall, such as the direct formation of low band gap compounds of arsenic tellurides.

A further advantage of the present method is that it provides controlled cap layer treatment compared to that disclosed in the prior art (see for example McCandless, B. E., Dobson, K. D., Solar Energy, 77 (2004) 839-856 and Potlog, T., Solar Energy Materials and Solar Cells, 80(3) (2003) 327-334) so as to leave a p+ surface, passivate the grain boundaries and promote grain enlargement within the absorber layer.

The above method may also be applied to manufacturing Tandem photovoltaic cells such as those described in Mahawela, P., Sivaraman, G., Jeedigunta, S.,

Gaduputi, J., Ramalingam, M., Subramanian, S., Vakkalanka, S., Ferekides, C. S.,

Morel, D. L., Materials Science and Engineering B, 116 (2005) 283-291. This is advantageous due to the relatively low growth temperature and high yield produced using the method of the present invention. Additionally, the method may be used to select a required band gap for a tandem device by selecting particular alloys.

According to a second aspect of the present invention there is provided a CdTe photovoltaic cell manufactured in accordance with the method of the first aspect of the present invention.

The photovoltaic cell of the second aspect of the present invention may incorporate any or all of the features of the first aspect of the present invention, as desired or as appropriate.

According to a third aspect of the present invention, there is provided a CdTe photovoltaic cell comprising an n-type CdS window layer; and a p-type CdTe absorber layer characterised in that the CdTe absorber layer is doped with arsenic.

Doping the absorber layer is beneficial because it controllably increases the majority carrier concentration (i.e., acceptors/holes) leading to the control of p-type doping of the absorber, and promote the formation of segregated low band gap arsenic tellurides.

Grains within the absorber layer, or any other layers grown, can be enlarged by varying the type of substrate, substrate temperature and/or the substrate template, thus reducing routes for diffusion and improving performance.

According to a fourth aspect of the present invention, there is provided a CdTe photovoltaic cell comprising an n-type CdS window layer; and a p-type CdTe absorber layer characterised in that the CdTe absorber layer is alloyed with zinc.

Alloying the absorber layer control its band gap and increase its flexibility for use in tandem cells.

According to a fifth aspect of the present invention, there is provided a CdTe photovoltaic cell comprising an n-type CdS window layer; a p-type CdTe absorber layer; and a layer of transparent conductive oxide (TCO).

Provision of the additional layer of TCO improves the conductivity of the front contact.

According to a sixth aspect of the present invention, there is provided a CdTe photovoltaic cell comprising an n-type CdS window layer; a p-type CdTe absorber layer and a high resistivity (high-p) layer.

The provision of the high resistivity (high-p) layer can help to avoid shunting effects of the absorber to the front transparent conductive oxide, thus improving the response of the cell.

According to a seventh aspect of the present invention, there is provided a CdTe photovoltaic cell comprising an n-type CdS window layer; a p-type CdTe absorber layer; and an additional highly p+ doped layer of p+ type material.

The provision of the highly p+ doped layer provides the advantage that the cell has a lower series electrical resistance. In such an embodiment, an all-in-one process other than wet etching may then be used for forming back contacts. In such cases, a heavily As-doped CdTe: As ⁺ may be particularly suitable for forming the highly p+

doped layer. Suitable doping concentrations might be in the range of 1x10 to

IxIO ⁺²¹ atoms.cm ^" .

According to an eighth aspect of the present invention, there is provided a CdTe photovoltaic cell comprising an n-type CdS window layer; a p-type CdTe absorber layer; and a CdCl ₂ cap layer, the device being annealed such that the CdCl ₂ cap layer acts to passivate the grain boundaries.

Passivating the grain boundaries improves the transport of carriers through the grains and reduces the recombination of charges at the boundaries.

The photovoltaic cells of the third, fourth, fifth, sixth and seventh aspects of the present invention may each be manufactured according to the method of the first aspect of the present invention and may each incorporate any or all of the features of the first or second aspects of the present invention, as desired or as appropriate.

In order that the invention may be more clearly understood, one embodiment will now be described further herein, by way of example only with reference to the accompanying drawings in which:

Figure 1 is a schematic diagram of an embodiment of a photovoltaic cell according to the present invention in a superstrate configuration; and

Figure 2 is a schematic diagram of an embodiment of a photovoltaic cell according to the present invention in a substrate configuration.

In a first example, a simple CdTe photovoltaic cell according to the present invention comprises an n-type CdS window layer; a p-type CdTe absorber layer; and a CdCl ₂ cap layer. The cell is manufactured by growing each successive layer by MOCVD in situ.

The cell is formed on a suitable superstrate or substrate, which is cleaned before processing is carried out. The layers are grown in a reduced pressure or atmospheric pressure horizontal or vertical MOCVD reactor. The thickness and growth characteristics of the layers are monitored during the process using a triple wavelength interferometer (e.g., wavelengths: 532nm, 635nm & 980nm).

In the specific process embodiment described in detail herein below, the in situ layer growths and annealing are carried out as follows:

1. CdS Window layer fa-type semiconductor): Dimethylcadmium (DMCd) and Ditertiarybutylsulfide (DtBS) organo-metallic precursors are used. The CdS layer is grown under H ₂ atmosphere at a substrate temperature of 315 ⁰ C. The layer has a II: VI precursor ratio of substantially 1. The total gas flow in the reactor is 3355 seem with a Cd partial pressure of 2.7 x 10 ^"4 atm. This results in a growth rate of 0.12 - 0.14 nm/s, which is allowed to continue until the layer is around 240 nm thick. The band gap energy (Eg) of the layer is around 2.53eV. 2. CdTe Absorber layer (p-type semiconductor): Dimethylcadmium (DMCd),

Diisopropyltelluride (DiPTe) and Tris(Dimethylamino)Arsine (tDMAAs)

organo-metallic precursors are used. This provides an arsenic doped cadmium telluride layer (CdTe:As). The arsenic doped layer is grown under hydrogen (H^) atmosphere at a substrate temperature of 39O ⁰ C and a ILVI precursor ratio of 1.82. The layer thickness at the point of monitoring was 2 μm in order to achieve 4 -5 μm thickness at 45 - 70 cm upstream. The total gas flow in the reactor is 4400 seem with a Cd partial pressure of 2 x 10 ^"4 atm. The doping is carried out using a double dilution line, where the partial pressure of Arsenic is kept at 1.5 x 10 atm. The uniform concentration of arsenic within the Cadmium telluride layer thickness is 8 x 1O ⁺¹⁸ atoms.cm ^"3 . The arsenic plays a crucial role in the p-type doping of the CdTe absorber layer. The growth rate is 0.4 - 0.44 nm/s. The band gap energy of this layer is 1.53eV.

3. Cap/treatment layer: Dimethylcadmium (DMCd) and Teriarybutylchloride (tBuCl) organo-metallics precursors are used. The cadmium chloride (CdCl ₂ ), grown at a substrate temperature of 300 ⁰ C, under hydrogen (H ₂ ) atmosphere, and a ILVII precursor ratio of 0.29 to a thickness of 450 nm. The total gas flow in the reactor is 3500 seem with a Cd partial pressure of 2.8 x 10 ^"4 atm giving a growth rate of 5.05 nm/s.

4. Annealing treatment of the fully grown device: at 400 ⁰ C for 10 mins under hydrogen (after 5 mins stabilisation period). The Chlorine (coming from the CdCl ₂ cap layer) diffuses through the grain boundaries. This allows the modification/passivation of the grain boundaries improving the transport of carriers through the grains and reducing the recombination of charges at the boundaries.

5. Cooling of device: under hydrogen to room temperature before being open to ambient air for metallisation and measurement of photo-electric characteristics.

After the continuous in situ process detailed above, the following ex situ processing steps may be carried out before J-V (Photo-electric) characterisation:

1. The cell is sliced into a plurality of individual 17 x 25 mm samples,

2. Two sides of each sample are then etched with a bromine methanol (BrMeOH - 2% Bromine) solution to reveal the indium tin oxide (ITO) front contacts. During this etching, the device area is masked by adhesive tape.

3. The BrMeOH solution is then diluted to obtain a 0.26% Br solution to etch the surface of the CdTe: As. This solution is applied for 5 seconds so as to remove 1 μm of the CdTe: As layer).

4. Gold contacts are evaporated from a gold wire, using a tungsten coil at a vacuum of 2 x 10 ^"5 Torr. A suitable mask is provided to in order that a desired plurality of gold contacts is formed.

Typically, the J-V characterization, of the finished device, can be carried out using an indium/gallium mixture for the front contact and deposited gold back contacts over a 2.5 cm ² activated cell. The gold contacts may be formed so as to provide: 10 round contacts (contact area: 2.49 x 10 ^" cm ); or 3 square contacts (each contact area: 26.5 x lθ ^"2 cm ² ).

It is possible and indeed preferable for cells according to the present invention to incorporate some additional optional features. Example of such photovoltaic cells according to the present invention which incorporate a number of optional features are shown in figure 1 (superstrate configuration) and figure 2 (substrate configuration).

Turning now to figure 1, the cell 100 comprises a transparent superstrate 101, a layer of transparent conductive oxide (TCO) 102, a high resistivity (high-p) layer 103, a front contact 104 formed upon the TCO layer, a window layer 105, an absorber layer 106, a highly p+ doped layer 107, a cap layer 108 and a back contact 109 provided upon said cap layer 108.

The superstrate may comprise any suitable transparent substance, such as glass or polymer. It might have a thickness of 1 mm.

As above, the superstrate is cleaned before processing is carried out. The later layers are grown in a reduced pressure or atmospheric pressure horizontal or vertical

MOCVD reactor. The thickness and growth characteristics of the layers are monitored during the process using a triple wavelength interferometer (e.g., wavelengths:

532nm, 635nm & 980nm).

The extra TCO layer 102 is an optional feature. If it is included, it can be beneficial because it can improve the conductivity of the front contact. The TCO might be any suitable TCO including Cadmium Stannate, cadmium oxide or doped tin oxide. The TCO layer 102 may have a thickness of 200 nm, which is sufficient to

improve the conductivity of the front contact while keeping the TCO layer relatively thin.

The high resistivity (high-p) layer 103 is an optional feature. It can help to avoid shunting effects. It may be formed from any suitable material such as Zinc Stannate, ZnO or ZnS. It may typically have a thickness of 60 nm.

The window layer 105 may be formed from CdS or Cd(Zn)S. It may additionally be doped with Cl or other group VII material (or indeed any other suitable donor). The window layer 105 would have a thickness in the range 0.02- 0.3 μm.

Optionally, a multilayer graded band gap (not shown) may be provided between the window layer 105 and the absorber layer 106. This can result in improved charge carrier collection and can also improve open-circuit voltage (Voc). This can be achieved by laying down a layer of CdSe. Typically this will have a thickness in the range 0.02-0.2μm.

The absorber layer 106 typically comprises CdTe or Cd(Zn)Te. It may however be doped with As or any other group V material (or other suitable acceptor). The absorber layer 106 would have a thickness in the range 0.6-0.5 μm.

The highly p+ doped layer 107, is formed from CdTe: As+ or of binary/tertiary alloys of Cd(Zn)Te doped with As and/or any other group V material (or other p-type dopant which will increase acceptor concentration). The highly p+ doped layer 107

may be 0.05-1.5um thick. Providing the highly p+ doped layer 107 lowers the resistance of the back contact 109.

The cap layer 108 is typically formed from CdCl ₂ . Beneficially, during the annealing process Chlorine (from the CdCl ₂ cap layer 108) can diffuse through the grain boundaries. This passivates the grain boundaries thus improving the transport of carriers through the grains and reducing the recombination of charges at the boundaries. The cap layer 108 is of thickness in the range 0.05 to 1 μm.

The device 100 is formed by use of CVD for formation of the layers. A number of variations on the CVD technique used are possible, which still result in a functional device. These are summarised in Table 1.

Table 1 - Possible Variations in CVD Technique

The device 100 (excluding superstate 101, TCO layer 102 and contacts 104, 109) can be formed by use of CVD in situ in the specific order and using the specific conditions set out in steps 1-5 of Table 2 (see end of description).

The front contacts 104 are also provided on the TCO layer 102 prior to device formation but are revealed after the in situ steps, typically by etching (at step 6 of Table 2). The front contact 104 may be formed by indium/gallium mixture or equivalent, preferably transparent and/or patterned. The etching may be carried out by any suitable technique water spray, physical or chemical etching including the use of a 2% Bromine Methanol (BrMeOH) solution.

The back contact 109 is formed upon the cap layer 108 (at step 7 of table 2). The contact 109 is typically metallic and may be formed from, for example, gold, Molybdenum, Nickel or similar. It may also be an alloy or mixture of two or more metals. It is typically formed by an evaporation process (in conjunction with a suitable mask) using a Tungsten coil (or other suitable means). This can be performed at a temperature in the range 280-460 ⁰ C and at a vacuum of around 2 x 10 ^{" 5} Torr. The back contact 109 should have a thickness in the range 0.005-1 μm.

Turning now to figure 2, the cell 200 is in a substrate configuration and thus whilst it comprises much the same layers as the cell 100 but there are some small differences in the order in which the layers are provided. Accordingly, the order in which the layers are formed would, of course, also vary. As would be apparent to the skilled man, the same conditions can be applied to the formation of each layer for the device 200 of figure 2 as for the device 100 of figure 1. For the sake of completeness, the layers would be formed on the substrate 201 in the following order: highly p+ doped layer 207; absorber layer 206; cap layer 208; window layer 205; optional high resistivity layer 203 and TCO 202.

One other variation is that as the direction of illumination is not through the substrate 201, the substrate 201 need not be transparent in the device 200 of figure 2.

It is of course to be understood that the invention is not to be restricted to the details of the above embodiment, which is described by way of example only.

Table 2 - Sequential steps and growth parameters for the manufacture of a device 100 as shown in figure 1 in a MOCVD chamber.

Kt

Kt