DE-JONGHE, Véronique (IP DepartmentHTC 60 1.31 Prof Holstlaan 4, AG Eindhoven, NL-5656, NL)
| CLAIMS:
1. A method of manufacturing a contact structure in a semiconductor device, the method comprising steps of: providing a substrate (1) covered with an insulating layer (3), the insulating layer (3) being provided with a contact hole (4) extending through the insulating layer (3) up to the substrate (1); providing a conductive layer (6) on the insulating layer (3) and in the contact hole (4); etching the conductive layer (6) in a planar way until the insulating layer (3) is reached such that the conductive layer (6) is left behind in the contact hole (4) for forming a contact (6); and etching back the conductive layer (6) during a predefined time period in such a manner, that a portion of the conductive layer (6) is left behind in the contact hole (4).
2. A method as claimed in claim 1, wherein, before the step of etching back the conductive layer (6), the contact structure is subjected to an inspection to determine location and dimension of a void or seam (8) in the contact (6), and wherein, in the step of etching back the conductive layer (6), the predefined time period is derived from the location and dimension of the void or seam (8), such that during the etching back of the conductive layer (6) the void or seam (8) is removed.
3. A method as claimed in claim 1 or 2, wherein, before the step of providing a conductive layer (6), a barrier layer (11) is provided on the insulating layer (3) and in the contact hole (4) covering all sidewalls of the contact hole (4), and wherein the step of etching the conductive layer (6) comprises a first sub-step of etching the conductive layer (6) until the barrier layer (11) is reached, and a second sub-step of etching the barrier layer (11).
4. A method as claimed in any one of claims 1 to 3, wherein, in the step of providing a substrate (1), the substrate has been provided with a DRAM memory cell, the DRAM memory cell comprising a transistor (9), the transistor (9) having a diffusion region (7), the transistor being covered with the insulating layer (3), and wherein the contact hole (4) is provided at a location in the diffusion region (7) to allow the contact (6) to be formed with the diffusion region (7).
5. A method as claimed in claim 4, wherein, after the step of etching back the conductive layer (6), a further insulating layer (13) is provided, after which a further hole (14) is formed in the further insulating layer (13) at the location in the diffusion region (7), the further hole (14) extending through the further insulating layer (13).
6. A method as claimed in claim 5, wherein a first electrode layer (15) is formed on all sidewalls of the further hole (14) and the sidewalls of exposed parts of the contact hole (4), after which a dielectric layer (16) is formed covering the first electrode layer (14), and after which a second electrode layer (17) is formed covering the dielectric layer (16), the first electrode layer (15) and the second electrode layer (17) forming a capacitance (10) for the DRAM memory cell.
7. A method of manufacturing a semiconductor device comprising the method as claimed in any one of claims 1 to 3, wherein the semiconductor device is provided with circuitry (9) in the substrate (1), and the semiconductor device is further provided with interconnections in the insulating layer (3) and the further insulating layer (13).
8. A method of manufacturing a DRAM memory comprising the method as claimed in any one of claims 4 to 6, wherein the DRAM memory is provided with a plurality of DRAM memory cells and with peripheral circuitry in the substrate (1), and the DRAM memory is further provided with interconnections in the insulating layer (3) and the further insulating layer (13). |
MANUFACTURING A CONTACT STRUCTURE IN A SEMICONDUCTOR
DEVICE
FIELD OF THE INVENTION
The invention relates to a method of manufacturing a contact structure in a semiconductor device. The invention further relates to a method of manufacturing a semiconductor device. The invention also relates to a method of manufacturing a DRAM memory.
BACKGROUND OF THE INVENTION
Due to the ever- increasing packing density of semiconductor devices, the line width gradually decreases in each subsequent process technology node. At the same time, the aspect ratio of line contacts increases. Accordingly, contact filling becomes more and more difficult. For example, in case of tungsten (W) contacts that are deposited, a void or a seam may be produced in the contact hole. The presence of a void or a seam increases the contact resistance, which is detrimental for the operation and reliability of the semiconductor device. To solve this problem, US 2006/0024950 proposes a method of forming a metal contact structure including steps of: forming an interlayer insulating layer on a substrate, etching the interlayer insulating layer to form a hole, depositing a metal layer on the surface of the interlayer insulating layer including inside the hole, planarizing the metal layer using chemical-mechanical-polishing (CMP) to provide a buried portion of the metal layer outside the hole, etching back the buried portion of the metal layer in the hole such that some of the portion of the metal layer in the hole is left behind, and depositing a conductive layer on the surface of the interlayer insulating layer and the portion of the metal layer that is left behind in the hole. The resulting contact structure provides a lower resistance.
A drawback of the method in US 2006/0024950 is that the cycle time is relatively long.
SUMMARY OF THE INVENTION
It is an object of the invention to provide a method of manufacturing a contact structure in a semiconductor device, which provides a shorter cycle time and thus a higher manufacturing throughput. The invention is defined by the independent claims. The dependent claims define advantageous embodiments.
The object of the invention is realized in that a method of manufacturing a contact structure in a semiconductor device is provided, the method comprising steps of: providing a substrate covered with an insulating layer, the insulating layer being provided with a contact hole extending through the insulating layer up to the substrate; providing a conductive layer on the insulating layer and in the contact hole; etching the conductive layer in a planar way until the insulating layer is reached such that the conductive layer is left behind in the contact hole for forming a contact; and - etching back the conductive layer during a predefined time period in such a manner, that a portion of the conductive layer is left behind in the contact hole.
By doing so, the last two steps of the method are of the same kind, which opens up the possibility to perform both steps in the same manufacturing tool. This saves one transition between two different tools, which in its turn reduces the cycle time of the method, which increases the throughput.
An advantageous embodiment of the method according to the invention is further defined in that, before the step of etching back the conductive layer, the contact structure is subjected to an inspection in order to determine location and dimension of a void or seam in the contact, and in that, in the step of etching back the conductive layer, the predefined time period is derived from the location and dimension of the void or seam, such that during the etching back of the conductive layer the void or seam is removed. This embodiment has the advantage that the removal of the void or seam can be optimized. When no voids or seams are present, or when the voids or seams do not extend deeply, less material needs to be etched away than in the case of voids and seams that extend more deeply. Preferably, before the step of providing a conductive layer, a barrier layer is provided on the insulating layer and in the contact hole, the barrier layer covering all sidewalls of the contact hole, and the step of etching the conductive layer comprises a first sub-step of etching the conductive layer until the barrier layer is reached, and a second sub- step of etching the barrier layer. Barrier layers can be used to encapsulate a conductive layer,
which may be needed in case particular metals are used, such as copper. Furthermore, barrier layers can also be used as etch stop layers to improve selective etching of the metallization layer.
Another embodiment of the method according to the invention is defined in that, in the step of providing a substrate, the substrate has been provided with a DRAM memory cell, the DRAM memory cell comprising a transistor, the transistor having a diffusion region, the transistor being covered with the insulating layer, and in that the contact hole is provided at a location in the diffusion region for allowing the contact to be formed with the diffusion region. This embodiment enables the manufacturing of (embedded) DRAM memories, wherein the invention can be particularly advantageous.
In a further embodiment of the method, after the step of etching back the conductive layer, a further insulating layer is provided after which a further hole is formed in the further insulating layer at the location in the diffusion region, the further hole extending through the further insulating layer. These steps prepare the formation of a capacitance for the DRAM memory cell right on top of the contact.
Preferably, in the latter embodiment, a first electrode layer is formed on all sidewalls of the further hole and the sidewalls of exposed parts of the contact hole after which a dielectric layer is formed covering the first electrode layer, and after which a second electrode layer is formed covering the dielectric layer, the first electrode layer and the second electrode layer forming a capacitance for the DRAM memory cell. Due to the method in accordance with the invention, the formation of the DRAM capacitance electrodes in the further hole and the exposed parts of the contact hole has improved drastically. This is caused by the fact that a void or a gap is no longer present in the top part of the contact, which reduces the risk of a short-circuit between the two electrodes. Additionally, the capacitance of the DRAM capacitance has increased because of the larger electrode areas, which improves the DRAM memory operation.
The invention further relates to a method of manufacturing a semiconductor device, wherein the semiconductor device is provided with circuitry in the substrate, and the semiconductor device is further provided with interconnections in the insulating layer and the further insulating layer. This method also greatly benefits from the shorter cycle time of the method of manufacturing a contact structure according to the invention. It must be noted that, nowadays, a semiconductor device may comprise up to 12 metallization layers and this number is expected to increase even further according to Moore's Law. In each metallization
layer the cycle time is reduced. In other words, the gain obtained by the invention will increase even further in the future.
The invention also relates to a method of manufacturing a DRAM memory, wherein the DRAM memory is provided with a plurality of DRAM memory cells and with peripheral circuitry in the substrate, and the DRAM memory further being provided with interconnections in the insulating layer and the further insulating layer. DRAM memories benefit greatly from the method according to the invention, because the risk of short-circuits in capacitance electrodes is reduced. A void or seam in the upper part of a contact on which the capacitance is manufactured will cause the electrodes and dielectric not to deposit (for example using an atomic layer deposition (ALD)) in a planar way, which may create short- circuits between the electrodes. Hence, next to the higher manufacturing throughput obtained by the invention, the reliability of the DRAM memories is greatly increased by the method according to the invention.
Any of the additional features can be combined together and combined with any of the aspects. Other advantages will be apparent to those skilled in the art. Numerous variations and modifications can be made without departing from the scope of the claims of the present invention. Therefore, it should be clearly understood that the present description is illustrative only and is not intended to limit the scope of the present invention.
BRIEF DESCRIPTION OF THE DRAWINGS
How the present invention may be put into effect will now be described by way of example with reference to the appended drawings, in which:
Fig. 1 illustrates a portion of a known DRAM memory cell in an intermediate stage of its manufacturing process; Fig. 2 illustrates a portion of a DRAM memory cell in a similar stage of its manufacturing process according to one embodiment of the method of the invention; and
Figs. 3 and 4 illustrate the same portion of a DRAM memory cell as Fig. 2, but in earlier stages of the method of manufacturing.
DETAILED DESCRIPTION OF THE DRAWINGS
The integration of a DRAM (Dynamic Random Access Memory) with logical functions allows rapid access to the information it contains. Even if the number of manufacturing operations increases with the addition of a DRAM on the same chip, we
obtain a single chip instead of 2. This explains the economic benefits of an "embedded DRAM" solution (eDRAM).
The DRAM-cell is composed of a capacitor to store information and a transistor acting as an on/off switch. The capacitor is usually created between the contact and the first metallization layer (metal 1). One of the important parameters for a DRAM memory is the capacitance:
C = (e r . e 0 . S) / d where: e 0 is the vacuum permittivity, - e r is the relative permittivity of the dielectric, d is the distance between the 2 electrodes, and
S is the surface area of the electrodes.
Referring to Fig. 1, this Figure shows a portion of a conventional DRAM memory cell in a stage of its manufacturing process. The DRAM memory cell comprises a transistor 9 and a capacitance 10. The transistor is formed by a gate 5 situated above a substrate 1, and diffusion regions 7 located in the substrate 1, wherein the diffusion regions 7 form a source region and a drain region during operation of the DRAM memory cell. On top of the transistor 9, an insulating layer 3 has been provided. In the insulating layer 3 contact holes 4 have been formed. In the contact holes 4 contacts 6 are present, each contact 6 extending towards the diffusion region 7 underneath. A further insulating layer 13 has been provided on top of the insulating layer 3. In the further insulating layer 13 further contact holes 14 have been formed. In one of the further contact holes 14 a stack of a first electrode layer 15, a dielectric layer 16, and a second electrode layer 17 has been formed on all sidewalls, which forms the capacitance 10 of the DRAM memory cell. The first electrode layer 15 is in electrical contact with the contact 6 in the contact hole 4 underneath.
In the most advanced DRAM technologies, the dimensions are so small that electrode deposition and the (high-k) dielectric deposition is usually done with an atomic layer deposition (ALD) process. In that case, a problem may be faced which is the fact that a void or seam 8 in the top part of the contact 6 is sometimes visible after chemical-mechanical polishing (CMP). In that case the electrode layers 15,16,17 fill the void or seam 8 and this may lead to shorts between the electrodes 15,17.
Referring to Fig. 2, this Figure shows a portion of a DRAM memory cell in a similar stage of its manufacturing process according to one embodiment of the method of the invention. However, in this memory cell the contacts 6 have been partially removed
including the void or seam 8 (Fig. 1) in the top part thereof. Parts of the original contact holes 4 have been reopened exposing parts of the original sidewalls. Thus, portions 6' of the contacts 6 are left behind in the contact holes 4. Also, the electrode layer 15,16,17 of the capacitance 10 have been formed on both the sidewalls of the further contact hole 14 and on the exposed part of the sidewalls of the contact hole 4. In the DRAM memory cell according to the invention, the electrode layers 15,16,17 have been formed in a uniform way. As a consequence of that the risk of shorts between the electrodes 15, 17 has been reduced. Other parts of the memory cell are similar to Fig. 1.
In embodiments of the present invention, the term "substrate" may include any underlying material or materials that may be used, or upon which a device, a circuit or an epitaxial layer may be formed. In other alternative embodiments, this "substrate" may include a semiconductor substrate such as e.g. a doped silicon, a gallium arsenide (GaAs), a gallium arsenide phosphide (GaAsP), an indium phosphide (InP), a germanium (Ge), or a silicon germanium (SiGe) substrate. The "substrate" may include for example, an insulating layer such as an SiO 2 or an S13N4 layer in addition to a semiconductor substrate portion. Thus, the term substrate also includes glass, plastic, ceramic, silicon-on-glass, silicon-on sapphire substrates. The term "substrate" is thus used to define generally the elements for layers that underlie a layer or portions of interest. Also, the "substrate" may be any other base on which a layer is formed, for example a glass or metal layer. Hence, this substrate layer can be any material, which is suitable for inlaying a damascene structure, including an oxide layer such as silicon dioxide or TEOS for example. It can be formed on top of other underlying layers, including substrates and semiconductor or conductive layers.
The diffusion regions 7 may be suicided (nickel suicide, cobalt suicide, etc) in order to reduce the sheet and contact resistance. Furthermore, the insulating layers 3 and 13 may comprise materials such as: silicon oxide (SiO 2 ), Black Diamond™, Orion™, Aurora™, Silk™, p-Silk™ and other low-dielectric constant materials which are investigated or in use in IC manufacturing processes. The insulating layers 3,13 can be made of one dielectric material or a combination of multiple layers of different dielectric materials. The insulating layer 3 and the further insulating layer 13 may be provided with an etch stop layer or a hard- mask layer 2,12. These layers 2,12 can be made of materials such assilicon nitride (SiN), silicon carbide (SiC), silicon carbon nitride (SiCN). The contacts 6 may comprise tungsten (W), alluminum (Al), or copper (Cu).
During further processing, the other further contact hole 14 in which no electrodes 15,16,17 have been formed can be filled with a further contact on top of the
contact 6 (not shown in Figures), after which metallization layers can be formed (not shown in Figures).
Figs. 3 and 4 and illustrate the same portion of a DRAM memory cell as Fig. 2, but in earlier stages of the method of manufacturing. Referring to Fig. 3, this Figure illustrates a stage in the substrate 1 (comprising the transistor 9 and all its components 5,7) has been provided wherein substrate 1 has been covered with an insulating layer 3, and wherein the insulating layer 3 has been provided with a contact hole 4 extending through the insulating layer 3 up to the substrate 1. Also, in this stage, the conductive layer 6 has been provided on the insulating layer 3 and in the contact hole 4. The conductive layer 6 comprises at least a void or a seam 8 in the upper part of one of the contact holes 4. Before the provision of the conductive layer 6, a barrier layer 11 may be provided. This barrier layer 11 may comprise materials and/or compositions such as a stack of titanium and titanium nitride (Ti/TiN). Also other materials/compositions are possible such as tungsten nitride (WN). Referring to Fig. 4, this Figure illustrates a (later) stage in which the invention clearly differs from the prior art. In US2006/0024950A1 the redundant material, located above the insulating layer 3, of the conductive layer 6 is removed with a chemical- mechanical polishing step, after which a pretreatment follows and then an etch-back step to remove the upper parts of the contacts 6. Thus, in this step, portions 6' of the conductive layer 6 are left behind in the contact holes 4.
However, in the method according to the invention the redundant material of the conductive layer 6, located above the insulating layer 3, is removed using an etching step. In case a barrier layer 11 has been provided below the conductive layer 6 the etching step comprises two sub-steps. For example, in a first sub-step the redundant material of the conductive layer 6 is removed using an end-point detection signal derived from landing on the barrier layer 11. And in a second sub-step the barrier layer 11 is removed selectively from the material of the conductive layer 6. In case tungsten is used for the conductive material 6 and Ti/TiN for the barrier material, then in the first sub-step the tungsten conductive layer 6 can be removed selectively from the Ti/TiN using a SF6/N2 chemistry for example. And in the second sub-step the Ti/TiN barrier layer 11 can be removed using a C12/N2/Ar chemistry for example. The etch-back of the contacts 6 can be carried out using an SF6-chemistry for example. During the etch-back step seams and voids are removed and the contact holes 4 are partly reopened. By doing so, the last two steps of the method are of the same kind, which opens up the possibility to perform both steps in the same manufacturing tool. And this saves
one transition between two different tools, which in its turn reduces the cycle time of the method, which increases the throughput.
The invention thus provides a method of manufacturing which provides a shorter cycle time and increases the output per unit time of the manufacturing process (higher throughput). The more metallization layers are used the more advantageous the invention becomes. The invention further provides a method of manufacturing a semiconductor device.
The invention also provides a method of manufacturing a DRAM memory, wherein the invention is particularly advantageous.
Although the example illustrated in the Figures is a DRAM memory cell, the invention is advantageous for any type of contact structures in a semiconductor device.
Where the word insulating has been mentioned in this specification electrically insulating is meant. Where etching techniques are discussed in this specification the skilled person may easily vary the etch chemistries.
The present invention has been described with respect to particular embodiments and with reference to certain drawings but the invention is not limited thereto but only by the claims. Any reference signs in the claims shall not be construed as limiting the scope. The drawings described are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn to scale for illustrative purposes. Where the term "comprising" is used in the present description and claims, it does not exclude other elements or steps. Where an indefinite or definite article is used when referring to a singular noun e.g. "a" or "an", "the", this includes a plural of that noun unless something else is specifically stated.
Furthermore, the terms first, second, third and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the invention described herein are capable of operation in other sequences than described or illustrated herein.