Title:
MANUFACTURING METHOD FOR SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR STRUCTURE
Document Type and Number:
WIPO Patent Application WO/2023/045129
Kind Code:
A1
Abstract:
The present disclosure provides a manufacturing method for a semiconductor structure and a semiconductor structure. The method comprises: providing a first preliminary substrate and a second substrate, the first preliminary substrate comprising a first base substrate and a recess in the first base substrate; at least sequentially forming a first insulating layer, a trap-rich layer and a second insulating layer on an exposed surface of the recess to obtain a first substrate; and bonding the first substrate and the second substrate by using a plane where surfaces of the first base substrate on two sides of the recess are located as a bonding interface, so as to obtain a bonding structure. According to the present disclosure, the trap-rich layer is isolated from the first base substrate by using the first insulating layer such that the trap-rich layer is not in direct contact with the first base substrate, and it is ensured that the trap-rich layer hardly re-crystallizes at a high temperature, so that good stability of the high-resistance performance of a device is ensured, and the presence of the trap-rich layer inhibits formation of a weak mobile charge accumulation region by a trap charge in the second insulating layer with an interface shallow region of the first base substrate.
More Like This:
Inventors:
LI RONGWEI (CN)
Application Number:
PCT/CN2021/138908
Publication Date:
March 30, 2023
Filing Date:
December 16, 2021
Export Citation:
Assignee:
SUZHOU HUATAI ELECTRONICS CO LTD (CN)
International Classes:
H01L21/762; H01L27/12
Foreign References:
| CN109003935A | 2018-12-14 | |||
| CN103460371A | 2013-12-18 | |||
| EP0621644A2 | 1994-10-26 | |||
| CN106233426A | 2016-12-14 | |||
| CN113130621A | 2021-07-16 | |||
| CN1535478A | 2004-10-06 |
Attorney, Agent or Firm:
KANGXIN PARTNERS, P.C. (CN)
Download PDF: