Title:
MASH SIGMA-DELTA MODULATOR AND D/A CONVERTER CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2012/127579
Kind Code:
A1
Abstract:
The present invention provides a MASH sigma-delta modulator which comprises an integral unit having an M-stage parallel integration unit for performing integral operation in parallel with respect to N data inputted from an upstream unit and outputting the data to a downstream unit, a derivative unit having a parallel derivative unit for computing a difference in adjoining overflow in the corresponding parallel integration unit of the integral unit while performing derivative operation in parallel with respect to the inputted difference and outputting the operation results to a downstream unit, and a parallel-series conversion unit for performing a parallel-series conversion on the output from the derivative unit, wherein a parallel integration unit in the first stage of the integral unit receives a single input data in parallel, and a parallel integration unit in each stage of the integral unit and a parallel derivative unit in each stage of the derivative unit perform the integral operation and the derivative operation for each stage within a single operation clock with a frequency of 1/N times that of the master clock frequency, and the parallel-series conversion unit outputs the results of the parallel-series conversion in synchronization with the master clock.
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Inventors:
OISHI KAZUAKI (JP)
Application Number:
PCT/JP2011/056622
Publication Date:
September 27, 2012
Filing Date:
March 18, 2011
Export Citation:
Assignee:
FUJITSU LTD (JP)
OISHI KAZUAKI (JP)
OISHI KAZUAKI (JP)
International Classes:
H03M3/04; H03M1/66; H03M7/32
Foreign References:
| JP2004260791A | 2004-09-16 |
Attorney, Agent or Firm:
AOKI, Atsushi et al. (JP)
Aoki 篤 (JP)
Aoki 篤 (JP)
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Claims: