Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
MASK AND METHOD FOR MAKING THE SAME, AND METHOD FOR MAKING SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2003/052803
Kind Code:
A1
Abstract:
A mask allowing an alignment of TTR method and a complementary division and having a high strength. A method for making the mask. A method for making semiconductor devices having high pattern accuracy. A stencil mask having, in four small regions (A-D) on a membrane, stripe beams (grids) (4) formed by etching a silicon wafer, wherein the stripes are symmetrically arranged about the center point of the membrane, and any one of the grids is connected to another grid or the silicon wafer around the periphery of the membrane (the support frame). A method for making the stencil mask. A method for making semiconductor devices by use of the stencil mask.

Inventors:
OMORI SHINJI (JP)
MORIYA SHIGERU (JP)
Application Number:
PCT/JP2002/012689
Publication Date:
June 26, 2003
Filing Date:
December 04, 2002
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
SONY CORP (JP)
OMORI SHINJI (JP)
MORIYA SHIGERU (JP)
International Classes:
G03C5/00; G03F1/20; G03F1/68; G03F9/00; (IPC1-7): H01L21/027; G03F1/16; G03F7/20; H01J37/147
Foreign References:
JP2003059819A2003-02-28
JP2000323372A2000-11-24
JPS61283121A1986-12-13
US20010046631A12001-11-29
JP2001052989A2001-02-23
JP2000357647A2000-12-26
US5849437A1998-12-15
Attorney, Agent or Firm:
Satoh, Takahisa (Miyaki Bldg. 4-2 Yanagibashi 2-chome Taito-ku, Tokyo, JP)
Download PDF: