CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] The present application claims benefit of U.S. Provisional Patent Application Serial No. 62/505,375, filed May 12, 2017, and U.S. Patent Application No. 15/712,770, filed September 22, 2017, both of which are herein incorporated by reference in their entirety.

TECHNICAL FIELD

[0002] Certain aspects of the present disclosure generally relate to electronic circuits and, more particularly, to parallel battery charging circuits.

BACKGROUND

[0003] Power management integrated circuits (power management ICs or PMICs) are used for managing the power requirement of a host system. A PMIC may be used in battery-operated devices, such as mobile phones, tablets, laptops, wearables, etc., to control the flow and direction of electrical power in the devices. The PMIC may perform a variety of functions for the device such as DC-to-DC conversion, battery charging, power-source selection, voltage scaling, power sequencing, etc. In some cases, the PMIC may include parallel battery charging circuits.

SUMMARY

[0004] Certain aspects of the present disclosure generally relate to techniques and apparatus for operating a parallel battery charging circuit capable of charging a battery.

[0005] Certain aspects of the present disclosure provide a battery charging circuit. The battery charging circuit includes a first charging circuit and a second charging circuit. The first charging circuit generally includes a first charging output connectable to a battery and a first converter to provide power to the first charging output. The second charging circuit generally includes a second charging output connectable to the battery, a second converter to provide power to the second charging output, a first transistor coupled between an output of the second converter and the second charging output, and a current-sensing circuit coupled to the output of the second converter to sense a current through the first transistor.

[0006] Certain aspects of the present disclosure provide a method of operating a battery charging circuit including a first charging circuit and a second charging circuit for concurrently charging a battery. The method generally includes driving a first converter in the first charging circuit, driving a second converter in the second charging circuit, and sensing a charging current for charging the battery from the second charging circuit, based on an output of the second converter, to effectively sense an input current for the second charging circuit.

[0007] Certain aspects of the present disclosure provide an apparatus for charging a battery. The apparatus generally includes first means for converting a first current; second means for converting a second current, the second means for converting being coupled to the first means for converting; and means for sensing a charging current for charging the battery from the second means for converting, based on an output of the second means for converting, to effectively sense an input current for the second means for converting.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] So that the manner in which the above-recited features of the present disclosure can be understood in detail, a more particular description, briefly summarized above, may be had by reference to aspects, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only certain typical aspects of this disclosure and are therefore not to be considered limiting of its scope, for the description may admit to other equally effective aspects.

[0009] FIG. 1 illustrates a block diagram of an example device that includes a battery charging circuit, according to certain aspects of the present disclosure.

[0010] FIG. 2A is a circuit diagram of an example master-slave battery charging circuit, in accordance with certain aspects of the present disclosure.

[0011] FIG. 2B illustrates example signal waveforms for the battery charging circuit of FIG. 2A, in accordance with certain aspects of the present disclosure. [0012] FIG. 3A is a circuit diagram of an example slave battery charging circuit in the master-slave battery charging circuit of FIG. 2A, illustrating slave charging current sensing, in accordance with certain aspects of the present disclosure.

[0013] FIG. 3B illustrates example signal waveforms for the battery charging circuit of FIG. 3 A, in accordance with certain aspects of the present disclosure.

[0014] FIG. 4 is a circuit diagram of an example slave battery charging circuit in the master-slave circuit of FIG. 2A, illustrating reverse current blocking associated with BATFET s, in accordance with certain aspects of the present disclosure.

[0015] FIG. 5 is a flow diagram of example operations for running a parallel battery charging circuit, in accordance with certain aspects of the present disclosure.

[0016] FIG. 6 illustrates adaptive input current limiting (AICL) and adaptive battery current limiting (ABCL).

[0017] FIG. 7 is an example circuit diagram illustrating the concept of ABCL, in accordance with certain aspects of the present disclosure.

DETAILED DESCRIPTION

[0018] Various aspects of the disclosure are described more fully hereinafter with reference to the accompanying drawings. This disclosure may, however, be embodied in many different forms and should not be construed as limited to any specific structure or function presented throughout this disclosure. Rather, these aspects are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Based on the teachings herein one skilled in the art should appreciate that the scope of the disclosure is intended to cover any aspect of the disclosure disclosed herein, whether implemented independently of or combined with any other aspect of the disclosure. For example, an apparatus may be implemented or a method may be practiced using any number of the aspects set forth herein. In addition, the scope of the disclosure is intended to cover such an apparatus or method which is practiced using other structure, functionality, or structure and functionality in addition to or other than the various aspects of the disclosure set forth herein. It should be understood that any aspect of the disclosure disclosed herein may be embodied by one or more elements of a claim.

[0019] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0020] As used herein, the term "connected with" in the various tenses of the verb "connect" may mean that element A is directly connected to element B or that other elements may be connected between elements A and B (i.e., that element ^ is indirectly connected with element B). In the case of electrical components, the term "connected with" may also be used herein to mean that a wire, trace, or other electrically conductive material is used to electrically connect elements A and B (and any components electrically connected therebetween).

AN EXAMPLE DEVICE

[0021] FIG. 1 illustrates an example device 100 in which aspects of the present disclosure may be implemented. The device 100 may be a battery-operated device such as a cellular phone, a personal digital assistant (PDA), a handheld device, a wireless device, a laptop computer, a tablet, a smartphone, etc.

[0022] The device 100 may include a processor 104 that controls operation of the device 100. The processor 104 may also be referred to as a central processing unit (CPU). Memory 106, which may include both read-only memory (ROM) and random access memory (RAM), provides instructions and data to the processor 104. A portion of the memory 106 may also include non-volatile random access memory (NVRAM). The processor 104 typically performs logical and arithmetic operations based on program instructions stored within the memory 106.

[0023] In certain aspects, the device 100 may also include a housing 108 that may include a transmitter 110 and a receiver 112 to allow transmission and reception of data between the device 100 and a remote location. For certain aspects, the transmitter 110 and receiver 112 may be combined into a transceiver 114. One or more antennas 116 may be attached or otherwise coupled to the housing 108 and electrically connected to the transceiver 114. The device 100 may also include (not shown) multiple transmitters, multiple receivers, and/or multiple transceivers.

[0024] The device 100 may also include a signal detector 118 that may be used in an effort to detect and quantify the level of signals received by the transceiver 114. The signal detector 118 may detect such signal parameters as total energy, energy per subcarrier per symbol, and power spectral density, among others. The device 100 may also include a digital signal processor (DSP) 120 for use in processing signals.

[0025] The device 100 may further include a battery 122 used to power the various components of the device 100. The device 100 may also include a power management integrated circuit (power management IC or PMIC) 124 for managing the power from the battery to the various components of the device 100. The PMIC 124 may perform a variety of functions for the device such as DC-to-DC conversion, battery charging, power-source selection, voltage scaling, power sequencing, etc. In certain aspects, the PMIC 124 may include a battery charging circuit (e.g., a master-slave battery charging circuit), as described below. The various components of the device 100 may be coupled together by a bus system 126, which may include a power bus, a control signal bus, and/or a status signal bus in addition to a data bus.

EXAMPLE SLAVE CHARGER INPUT CURRENT SENSING

[0026] In order to charge the battery (e.g., battery 122) in a portable device, a battery charging circuit may be utilized. For certain aspects, the battery charging circuit may reside in a PMIC (e.g., PMIC 124). The battery charging circuit may comprise two or more parallel charging circuits, each capable of charging the battery, which may be connected together and to the battery in an effort to provide fast charging of the battery. The parallel charging circuits can be configured so that these circuits do not adversely interfere with each other during battery charging (e.g., in a master-slave relationship). Example master-slave battery charging circuits are described in U.S. Patent No. 9,590,436 to Sporck et al, filed April 11, 2014 and entitled "Master-Slave Multi-Phase Charging," herein incorporated by reference in its entirety. Two example parallel charging architectures include connection of: (1) a USBIN terminal on the master charging circuit to a VIN terminal on the slave charging circuit (VIN_s) (referred to as a "USBIN-VIN configuration"); or (2) a MID terminal on the master charging circuit (MID m) to a MID terminal on the slave charging circuit (MID s) (referred to as a "MID-MID configuration").

[0027] In contemporary charger designs on the market, the slave charging circuit may use a front porch field-effect transistor (FPFET) to handle: (1) input current sensing and (2) reverse current blocking of a leakage path from the battery to the power input while charging is disabled. This is typically done because the charger normally provides power (at a VPH PWR terminal) while charging is disabled. The FPFET is operating in a high voltage (HV) condition, and such HV circuitry takes up significant area (e.g., > 1 mm ² ) in a portable device. A VSYS terminal of the slave charging circuit (VSYS s) may be separated from the VPH PWR terminal of the master charging circuit by two battery field-effect transistors (BATFETs), and this VSYS s terminal may have no system load demand. Thus, when charging is disabled, the charger need not keep VSYS_s biased.

[0028] There may be several problems associated with traditional slave charging circuits (either USBIN-VIN or MID-MID configuration). For example, the FPFET and its gate control and current-sensing circuitry (operating in the HV domain) may take up significant area (e.g., -15% of the total die area). Being in the input current path of the slave charging circuit, the FPFET also has a power loss associated therewith. Furthermore, input current control for the slave charging circuit may either be complicated (in the USBIN-VIN configuration) or not functional (in the MID-MID configuration).

[0029] Certain aspects of the present disclosure provide a battery charging circuit that removes the FPFET for the slave charging circuit and provides support for a USBIN-to-VIN connection. Other small circuitry may be used to handle input current sensing and reverse current blocking. In this manner, the area of the removed FPFET and corresponding circuitry may be saved, and the USBIN-to-VIN connection is an option for board-level layout flexibility.

[0030] FIG. 2A is a circuit diagram of an example master-slave battery charging circuit 200, in accordance with certain aspects of the present disclosure. The master- slave battery charging circuit 200 includes a master charging circuit 202 and a slave charging circuit 204 for charging battery 205 and capacitor CBAT. This circuit 200 may support a USBIN-to-VIN_s connection and eliminate the FPFET for the slave charging circuit (FPFET s). The circuit 200 may effectively generate input current feedback based on BATFET s current (charge current) feedback, as described in greater detail below. Control circuity may be added in an effort to use BATFET s as a blocking FET when charging is disabled, as also described in greater detail below. This is possible because VSYS_s does not see any load when charging is disabled. While the circuit 200 can support USBIN-VIN without a FPFET_s, the circuit 200 can also support the traditional MID-MID configuration if desired, as indicated by the dashed line 206.

[0031] The master charging circuit 202 includes a FPFET m, a DC/DC converter circuit comprising a high-side FET (HSFET m) and a low-side FET (LSFET m), and a BATFET m. The slave charging circuit 204 includes: (1) a DC/DC converter circuit comprising a high-side FET (HSFET s) and a low-side FET (LSFET s) and (2) a BATFET s. The VIN s terminal (also referred to as the MID s terminal) may be connected to the drain of HSFET s, the source of HSFET s may be connected to the SW s terminal and to the drain of LSFET s, and the source of LSFET s may be connected to a reference potential (e.g., electrical ground) for the slave charging circuit 204. The gate of HSFET s may be driven by HSON s, while the gate of LSFET s may be driven by LSON s (not shown). Both HSON s and LSON s may be generated by a pulse-width modulator (not shown in FIG. 2A) such that HSFET s, LSFET s, and inductor Ls may operate as a synchronous buck converter.

[0032] The circuit 200 may also include external components (e.g., external to the ICs for the master charging circuit 202 and/or the slave charging circuit 204. For example, external components associated with the master charging circuit 202 may include: (1) a capacitor CMID m connected to the MID ra terminal and (2) an inductance-capacitance (LC) circuit comprising an inductor Lm and a capacitor CSYS m, with an input connected to the SW m terminal and an output connected to the VSYS_m terminal. External components associated with the slave charging circuit 204 may include: (1) a capacitor CMID_s connected to the VIN_s (MID_s) terminal and (2) an inductor Ls connected between the SW_s terminal and the VSYS_s terminal.

[0033] Compared to contemporary master-slave battery charging circuits, the circuit 200 may have no capacitor or a small capacitor (CSYS_s, not shown) connected to the VSYS s terminal. This may be to guarantee that BATFET s sees a similar current as the inductor Ls and HSFET s while HSFET s is turned on (e.g., while HSON s is logic high), for the purpose of current-sensing with BATFET s, instead of with a nonexistent FPFET s. Sample circuitry and a filter (as illustrated in FIG. 3A and described below) may be added to the slave charging circuit 204 for charge current feedback. For reverse blocking for certain aspects, BATFET s may be placed in an off state when charging is disabled by the bulk switch control circuit 208 and the gate blocking control circuit 210.

[0034] FIG. 2B is a plot 250 of example signal waveforms for the battery charging circuit 200 of FIG. 2A, in accordance with certain aspects of the present disclosure. Illustrated are HSON s (the gate drive signal for HSFET s), I_HS_s (the current through HSFET s), IIN s (the input current from the USBIN terminal to the capacitor CMID s), and ICHG s (the current through BATFET s and out of the CHGOUT terminal of the slave charging circuit 204). Although IIN_s remains nearly constant, I HS s increases while HSFET s is turned on (while HSON s is logic high) and then drops to zero when HSFET s is turned off (while HSON s is logic low). The inductor Ls prevents ICHG s from changing instantaneously, and thus, ICHG s increases with time while HSON_s is logic high and decreases with time while HSON_s is logic low (and LSON s is logic high). This sawtooth-shaped current signal for ICHG s is referred to in the field of power supplies as ripple current.

[0035] The effective input current feedback based on replicated BATFET s current sensing is described with respect to the example slave charging circuit 300 of FIG. 3A and the plot 350 of FIG. 3B illustrating example waveforms associated therewith. The slave charging circuit 300 may be incorporated into the battery charging circuit 200 of FIG. 2 and replace at least a portion of the slave charging circuit 204. In a parallel charging configuration, the slave charger's DC/DC converter output (VSYS_s) may be used solely for providing charging current for the battery (as opposed to also powering other components, as in the case of VPH PWR). Thus, charging current through the slave BATFET s (ICHG s) is the output current of the slave charger DC/DC converter with VSYS capacitor (CSYS_s) removed.

[0036] A simple and accurate solution to effectively sense the input current for the slave charger may be provided by a current-sensing circuit 301. The current-sensing circuit 301 may include a sensing FET (SNSFET_s), an amplifier 304, a charging current feedback FET (ICHG FB s), a current-sensing resistor (RSNS), two switches (SI and S2), and a resistor-capacitor (RC) filter (comprising resistor RFIL and capacitor CFILT). The signals for driving HSFET s and LSFET s (namely HSON s and LSON s) may be generated by and output from a control circuit 302. The drain of SNSFET_s may be connected with the VSYS_s terminal, which is also connected with the drain of BATFET s. The gates of BATFET s and SNSFET s may be connected together and controlled by a gate control signal BATFET G s. BATFET G s may be output by the control circuit 302 or by gate blocking control circuit 210 (which may be part of the control circuit 302). The bodies of BATFET s and SNSFET s may be connected together and controlled by the bulk switch control circuit 208 (which may be separate from or incorporated into the control circuit 302). The source of BATFET s may be connected with an input terminal (e.g., the positive terminal) of the amplifier 304, and the source of SNSFET s may be connected with another input terminal (e.g., the negative terminal) of the amplifier and with the source of ICHG FB s. The output of the amplifier 304 may be connected with the gate of ICHG FB s, and the drain of ICHG FB s may be connected with one terminal of resistor RSNS. In this manner, amplifier 304 will drive the gate of ICHG FB s so that voltages at the sources of BATFET s and SNSFET s are equal (e.g., equal within an offset voltage parameter of the amplifier). Thus, with the drains and gates of BATFET s and SNSFET s also having the same voltages, the drain-to-source currents through BATFET s and SNSFET_s should be nearly equal (e.g., within 5% of each other). Thus, the current through ICHG FB s (replicating the actual charging current through BATFET s) may be sensed by the resistor RSNS to provide a measurement of ICHG s as feedback for the control circuit 302.

[0037] With this circuit 300, gate control signal HSON_s is logic high to turn on HSFET s. Sample switch S I for sampling ICHG FB s through resistor RSNS is closed by control signal HSON LV (a low-voltage version of HSFET s gate driver HSON s, which may be generated by the control circuit 302) while HSFET s conducts current. Electrical ground (GND) sample switch S2 is open during this interval, and thus, the node labeled "IINT" increases in voltage with time as the current ICHG FB s ramps up with time. HSON LV is logic low when HSFET s is turned off (HSON s goes low), and HSON B is logic high. During this interval, switch SI is open, and switch S2 is closed by control signal HSON B to pull the node labeled "IINT" to ground. Designed to be roughly the inverse of HSON LV, HSON B may also be generated by the control circuit 302. The RC network is used to filter out high- frequency components and generate effective input current feedback signal IIN FB s, a voltage signal. Indicative of a current signal approximating IIN s, IIN FB s may be converted to a digital signal by an analog-to-digital converter (ADC) and processed by the control circuit 302. The control circuit 302 may adjust the duty cycles of the HSON_s and LSON_s gate drive signals based on IIN_FB_s to regulate the charging current ICHG s. One source of error may be due to the charge current sense amplifier bandwidth limit and feedback delay, which may be mitigated by a delayed HSON LV control signal, delayed with respect to HSON_s.

[0038] One alternative solution for input current sensing without FPFET s is to sense the input current through HSFET s, rather than based on current through BATFET s. However, with BATFET s current sensing, the circuitry is implemented in a medium-voltage (MV) domain, rather than a high-voltage (HV) domain. Circuitry for the MV domain may take up much smaller area than the same circuitry for the HV domain. Furthermore, compared to un-compensated HSFET s current sensing, BATFET s current sensing may not see the errors contributed by blanking time, due to amplifier output slew rate during HSON s.

[0039] For certain aspects, the slave charger may provide for reverse current blocking of a leakage path from the battery to the power input while charging is disabled. FIG. 4 is a circuit diagram of an example slave charging circuit 400, illustrating reverse current blocking associated with BATFET s, in accordance with certain aspects of the present disclosure. The slave charging circuit 400 may be incorporated into the battery charging circuit 200 of FIG. 2 and replace at least a portion of the slave charging circuit 204. For certain aspects, a portion of the slave charging circuit 400 may be combined with a portion of the slave charging circuit 300.

[0040] The slave charging circuit 400 includes switches S3, S4, S5, and S6. Switches S3 and S5 may be controlled by a charging enabled control signal (en_chrg), while switches S4 and S5 may be controlled by a charging disabled control signal (enb_chrg). These control signals may be generated by the control circuit 302 or by the bulk switch control circuit 208 (which may be part of the control circuit 302 for certain aspects). Although enb_chrg is approximately the inverse of en_chrg, the rising edge of enb_chrg may lag the falling edge of en_chrg, and the falling edge of enb_chrg may lead the rising edge of en_chrg, to effectuate break-before-make switching and avoid shorting the CHGOUT terminal to ground.

[0041] In parallel charging configurations, when charging is disabled (en chrg is logic low and enb chrg is logic high), BATFET s can be turned off because of no system current (e.g., the VSYS_s terminal is not loaded). In this condition, both HSFET s and LSFET s are turned off, switches S3 and S5 are open, and switches S4 and S6 are closed. Thus, BATFET s is configured in a blocking state by pulling both the gate and bulk terminals of BATFET s to ground, as illustrated in FIG. 4. This effectively blocks the reverse leakage from CHGOUT to VIN s (MID s), which may have been handled by FPFET s in traditional chargers. When charging is resumed (en_chrg is logic high and enb_chrg is logic low), switches S3 and S5 are closed, and switches S4 and S6 are open. Thus, the source and bulk terminals of BATFET s are connected together, and the gate terminal of BATFET s may be connected to the control signal BATFET G s.

[0042] Without a slave FPFET, the slave charging circuit described herein still provides effective input current sensing and reverse blocking. By using a small or no VSYS capacitor, the BATFET s current (i.e., ICHG s) may be a suitable representation of the inductor current in the slave DC/DC converter. A (delayed) internal MV level high-side FET on signal (e.g., HSON LV) may be used to sample the replicated battery current and generate a feedback signal while HSFET s is turned on. This method may provide around 5% input current accuracy based on existing operating conditions (1 to 5 A). For reverse blocking, both the BATFET s gate and body may be pulled down to ground, while charging is disabled, to block any current path from CHGOUT to VIN s (MID_s). This serves as a way to block battery leakage to VIN_s (MID_s) when VIN_s (MID s) is lower than the battery voltage.

[0043] FIG. 5 is a flow diagram of example operations 500 for running a parallel battery charging circuit, in accordance with certain aspects of the present disclosure. The operations 500 may be performed by a parallel battery charging circuit, such as the master-slave battery charging circuit 200 of FIG. 2A with a slave charging circuit including portions from FIG. 2 A, 3 A, and/or 4. [0044] The operations 500 may begin, at block 502, with the battery charging circuit driving a first converter (e.g., the synchronous buck converter that includes HSFET m, LSFET m, inductor Lm, and capacitor CSYS m) in a first charging circuit (e.g., the master charging circuit 202). At block 504, the battery charging circuit may drive a second converter (e.g., the synchronous buck converter that includes HSFET s, LSFET s, and inductor Ls) in a second charging circuit (e.g., the slave charging circuit 204). At block 506, the battery charging circuit may sense a charging current (e.g., ICHG_s) for charging a battery (e.g., battery 205) from the second charging circuit, based on an output (e.g., VSYS_s) of the second converter, to effectively sense an input current (e.g., IIN_s) for the second charging circuit. As used herein, sensing a charging current may refer to sensing the charging current directly or indirectly (e.g., sensing a replica of the charging current).

[0045] According to certain aspects, the second charging circuit includes a first transistor (e.g., BATFET s) coupled between the output of the second converter and the battery, a second transistor (e.g., SNSFET_s) coupled to the output of the second converter, a sensing resistor (e.g., resistor RSNS), a third transistor (e.g., ICHG_FB_s) coupled between the second transistor and the sensing resistor, and an amplifier (e.g., amplifier 304). The amplifier may have a first input coupled to the first transistor, a second input coupled to a node between the second transistor and the third transistor, and an output coupled to the third transistor. For certain aspects, sensing the charging current (to effectively sense the input current) at block 506 may entail sensing a replica of the charging current (e.g., the current through ICHG FB s). In this case, sensing the charging current (to effectively sense the input current) at block 506 may involve driving a gate of the first transistor and a gate of the second transistor with a same gate voltage and driving a gate of the third transistor with the output of the amplifier such that a first voltage at the first input is equal to a second voltage at the second input. For certain aspects, sensing the charging current (to effectively sense the input current) at block 506 may include closing a first switch (e.g., switch SI) having a terminal coupled to the third transistor and to the sensing resistor during a first interval (e.g., HSON_LV is logic high) and opening the first switch during a second interval (e.g., HSON_LV is logic low). In this case, the first and second intervals may be based on timing of a control signal (e.g., HSON_s) for a high-side transistor (e.g., HSFET_s) in the second converter. For certain aspects, sensing the charging current (to effectively sense the input current) at block 506 may further involve opening, during the first interval, a second switch (e.g., switch S2) coupled between another terminal of the first switch and a reference potential node (e.g., ground) of the second charging circuit, closing the second switch during the second interval, and low-pass filtering a voltage signal (e.g., voltage at the node labeled "IINT") at the other terminal of the first switch during the first and second intervals. In this case, the filtered voltage signal (e.g., IIN_FB_s) may represent the input current (e.g., IIN_s) for the second charging circuit. For certain aspects, the operations 500 may further include controlling the second converter based on the sensed charging current to adjust the charging current (as well as the input current) from the second charging circuit. For certain aspects, the operations 500 may further entail disabling charging by the battery charging circuit; disconnecting a gate of the first transistor from a control signal (e.g., BATFET G s); connecting the gate of the first transistor to a reference potential node (e.g., ground) for the second charging circuit; disconnecting a body of the first transistor from a source of the first transistor; and connecting the body of the first transistor to the reference potential node for the second charging circuit. For certain aspects, the operations 500 may further involve enabling charging by the battery charging circuit; disconnecting the gate of the first transistor from the reference potential node for the second charging circuit; connecting the gate of the first transistor to the control signal; disconnecting the body of the first transistor from the reference potential node for the second charging circuit; and connecting the body of the first transistor to the source of the first transistor.

[0046] According to certain aspects, the second converter includes a first transistor (e.g., HSFET s), a second transistor (e.g., LSFET s) coupled to the first transistor, and an inductor (e.g., inductor Ls) having a terminal (e.g., the SW_s terminal) coupled to a node between the first and second transistors and another terminal (e.g., the VSYS_s terminal) coupled to the output of the second converter. In this case, a capacitor coupled to the other terminal of the inductor is absent from the second converter.

[0047] According to certain aspects, the operations 500 further entail controlling the second converter based on the sensed charging current, at optional block 508. In this case, the second converter may include a first transistor (e.g., HSFET s), a second transistor (e.g., LSFET s) coupled to the first transistor, and an inductor (e.g., inductor Ls) having a terminal (e.g., the SW_s terminal) coupled to a node between the first and second transistors and another terminal (e.g., the VSYS_s terminal) coupled to the output of the second converter. For certain aspects, controlling the second converter at block 508 may include adjusting duty cycles of signals driving gates of the first and second transistors, based on the sensed charging current. In this manner, the charging current (as well as the input current) may be regulated with feedback.

[0048] There are several advantages and benefits to the slave charging circuits described herein. For example, significant area (e.g., > 1 mm ² ) may be saved by removing FPFET s and related circuitry, which may be more than 15% of the total area of conventional slave chargers. Most of the existing core circuitries for BATFET control and charger current sensing may be re-used, with the addition of small sample circuitry and digital control. HV circuitry biasing for FPFET s and input current sensing may be removed, and the design of the parallel charger is simplified. Certain aspects of the present disclosure support either a MID-VIN (utilize master charger's FPFET m) or USBIN-VIN connection. The system solution is simplified, and a relatively large VSYS capacitor (CSYS_s) is eliminated, which may be -20 μΡ for contemporary chargers. Furthermore, there may be unified trim procedures for charger current and input current sensing, such that only one trim step is performed.

EXAMPLE ADAPTIVE BATTERY CURRENT LIMITING

[0049] FIG. 6 provides a graph 600 illustrating the concept of adaptive input current limiting (AICL). AICL reduces the input current (UN) from a travel adapter (TA) 602 to a battery charger 604 in digital increments (±ΔΙΙΝ), thereby preventing TA output voltage collapse, which in turn may maximize power from the TA. When TA collapse occurs, the output voltage VSUBIN falls drastically in the constant-current (CC) region, as illustrated in the graph 600. With AICL, IIN is reduced incrementally until the output voltage is above a voltage threshold (V-AICL). Eliminating the slave FPFET in a parallel battery charger (as described above) may make it difficult to implement AICL and prevent TA collapse (especially when using low-cost, low-performance AC/DC TAs), and also to minimize thermal profile, which is desired for implementing the fastest battery charging.

[0050] Certain aspects of the present disclosure provide techniques and apparatus for implementing adaptive battery current limiting (ABCL), in an effort to prevent TA collapse. ABCL involves modulating the battery current (IBAT) (e.g., through BATFET s in the slave charging circuit) instead of the input current (UN) (e.g., through the absent FPFET s in the slave charging circuit), as in the case of AICL.

[0051] FIG. 7 is a block diagram of an example circuit 700 illustrating the concept of ABCL, in accordance with certain aspects of the present disclosure. The AICL method through the FPFET m (illustrated by its drain-to-source on-resi stance) with current IAICL is illustrated in the main charging circuit 702 (e.g., the master charging circuit 202). The ABCL method is illustrated on the parallel charging circuit 704 (e.g., the slave charging circuit 204), which involves the current I ABCL through the slave battery field-effect transistor (BATFET s). Because the parallel charging circuit 704 has no system load (e.g., at the VSYS_s terminal), the BATFET_s current-sensing element (e.g., current-sensing circuit 301) can be used. And because the TA collapse affects both the main and parallel charging circuits 702, 704, the input collapse may be controlled directly by modulating the current through BATFET s.

[0052] Programmability of the battery current via BATFET s allows the battery current to scale, create a facsimile of actual input current (IABCL*Ratio), and balance the load on the TA 602 of the main and parallel charging circuits 702, 704. This main/parallel load allocation may be maintained during TA collapse. The Ratio may be proportional to approximately V-BAT / V-IN, where V-BAT is the battery voltage and V-IN is the output voltage of the TA 602, which is also the input voltage to the main and parallel charging circuits 702, 704. The battery current may be stepped (e.g., decremented) in any of various suitable increments, such as 25, 50, or 100 mA steps. The time between battery current steps may be any of various suitable intervals, such as 2.5, 5, 15, or 20 ms. ABCL may also use a programmable deglitch time of any suitable length, such as 30 μβ, 1 ms, 3 ms, or 10 ms.

[0053] During operation of the circuit 700, the parallel charging circuit 704 may determine that V-IN has fallen below the ABCL threshold voltage (V-ABCL). V- ABCL may be considered as being analogous to V-AICL in the graph 600, but for ABCL instead of AICL. Based on the determination that V-IN is less than V-ABCL, a counter may be triggered to begin counting. The duty cycles of the gate drive signals may be incrementally adjusted (e.g., using pulse-width modulation (PWM)) to reduce IABCL through BATFET s (according to the selected step-down size). After V-IN from the TA 602 is determined to be above V-ABCL, the counter may be stopped, and the duty cycles of the gate drive signals may stay at the adjusted value. In this manner, duty-cycle control of the sensed battery current may be employed to prevent input collapse of the TA 602.

[0054] Returning to FIG. 5, according to certain aspects, the operations 500 further involve sensing an input voltage at an input of the second converter, determining that the input voltage is below a threshold voltage, and controlling the second converter based on the determination. For certain aspects, the second converter includes a first transistor, a second transistor coupled to the first transistor, and an inductor having a terminal coupled to a node between the first and second transistors and another terminal coupled to the output of the second converter. In this case, controlling the second converter may include incrementally adjusting duty cycles of signals driving gates of the first and second transistors to incrementally decrease the charging current until the input voltage is determined to be above the threshold voltage. This may include using pulse-width modulation, for example.

[0055] The ABCL described herein provides a means to indirectly control the TA output current (UN = IAICL + IABCL*Ratio), and thus prevent input voltage collapse to the battery charger, by dynamically modulating the battery charging current. This technique allows the charger to eliminate the large input current sense FET (FPFET s), which is employed by previous generation parallel chargers.

[0056] The various operations of methods described above may be performed by any suitable means capable of performing the corresponding functions. The means may include various hardware and/or software component(s) and/or module(s), including, but not limited to a circuit, an application-specific integrated circuit (ASIC), or processor. Generally, where there are operations illustrated in figures, those operations may have corresponding counterpart means-plus-function components with similar numbering.

[0057] For example, first means for converting a first current may include a DC/DC converter, such as a buck converter in a charging circuit (e.g., HSFET m, LSFET m, and Lm in master charging circuit 202 as illustrated in FIG. 2A). Second means for converting a second current may include a DC/DC converter, such as a buck converter in a charging circuit (e.g., HSFET s, LSFET s, and Ls in slave charging circuit 204 as depicted in FIG. 2A). Means for sensing a charging current may include a current- sensing circuit (e.g., current-sensing circuit 301 as depicted in FIG. 3A). Means for regulating the charging current may include one or more transistors (e.g., HSFET s and/or LSFET s as illustrated in FIGs. 2A, 3A, and 4), one or more control signals (e.g., gate drive signal(s)) for the transistor(s), such as HSON_s and/or LSON_s as shown in FIG. 3A), and/or a control circuit (control circuit 302 as depicted in FIG. 3A) for producing the control signal(s). Means for blocking a reverse current may include a transistor (e.g., BATFET s as illustrated in FIGs. 2A, 3A, and 4), a control signal for a substrate (i.e., body or bulk) of the transistor, and/or a control circuit (e.g., switches S5 and S6 as depicted in FIG. 4 and/or control circuit 302 as illustrated in FIG. 3A) for generating the control signal. Means for sensing an input voltage, means for comparing the input voltage to a threshold voltage, and/or means for incrementally decreasing the charging current may include a control circuit (e.g., control circuit 302 as illustrated in FIG. 3 A) for producing one or more control signals (e.g., gate drive signal(s)) for the transistor(s), such as HSON_s and/or LSON_s as shown in FIG. 3A).

[0058] As used herein, the term "determining" encompasses a wide variety of actions. For example, "determining" may include calculating, computing, processing, deriving, investigating, looking up (e.g., looking up in a table, a database, or another data structure), ascertaining, and the like. Also, "determining" may include receiving (e.g., receiving information), accessing (e.g., accessing data in a memory), and the like. Also, "determining" may include resolving, selecting, choosing, establishing, and the like.

[0059] As used herein, a phrase referring to "at least one of a list of items refers to any combination of those items, including single members. As an example, "at least one of: a, b, or c" is intended to cover: a, b, c, a-b, a-c, b-c, and a-b-c, as well as any combination with multiples of the same element (e.g., a-a, a-a-a, a-a-b, a-a-c, a-b-b, a- c-c, b-b, b-b-b, b-b-c, c-c, and c-c-c or any other ordering of a, b, and c).

[0060] The various illustrative logical blocks, modules and circuits described in connection with the present disclosure may be implemented or performed with a general purpose processor, a digital signal processor (DSP), an ASIC, a field programmable gate array (FPGA) or other programmable logic device (PLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but in the alternative, the processor may be any commercially available processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

[0061] The methods disclosed herein comprise one or more steps or actions for achieving the described method. The method steps and/or actions may be interchanged with one another without departing from the scope of the claims. In other words, unless a specific order of steps or actions is specified, the order and/or use of specific steps and/or actions may be modified without departing from the scope of the claims.

[0062] The functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in hardware, an example hardware configuration may comprise a processing system in a wireless node. The processing system may be implemented with a bus architecture. The bus may include any number of interconnecting buses and bridges depending on the specific application of the processing system and the overall design constraints. The bus may link together various circuits including a processor, machine-readable media, and a bus interface. The bus interface may be used to connect a network adapter, among other things, to the processing system via the bus. The network adapter may be used to implement the signal processing functions of the physical (PHY) layer. In the case of a user terminal, a user interface (e.g., keypad, display, mouse, joystick, etc.) may also be connected to the bus. The bus may also link various other circuits such as timing sources, peripherals, voltage regulators, power management circuits, and the like, which are well known in the art, and therefore, will not be described any further.

[0063] The processing system may be configured as a general-purpose processing system with one or more microprocessors providing the processor functionality and external memory providing at least a portion of the machine-readable media, all linked together with other supporting circuitry through an external bus architecture. Alternatively, the processing system may be implemented with an ASIC with the processor, the bus interface, the user interface in the case of an access terminal), supporting circuitry, and at least a portion of the machine-readable media integrated into a single chip, or with one or more FPGAs, PLDs, controllers, state machines, gated logic, discrete hardware components, or any other suitable circuitry, or any combination of circuits that can perform the various functionality described throughout this disclosure. Those skilled in the art will recognize how best to implement the described functionality for the processing system depending on the particular application and the overall design constraints imposed on the overall system.

[0064] It is to be understood that the claims are not limited to the precise configuration and components illustrated above. Various modifications, changes and variations may be made in the arrangement, operation and details of the methods and apparatus described above without departing from the scope of the claims.