Title:
MATRIX MULTIPLIER, DATA PROCESSING METHOD, INTEGRATED CIRCUIT DEVICE, AND PROCESSOR
Document Type and Number:
WIPO Patent Application WO/2021/120711
Kind Code:
A1
Abstract:
A matrix multiplier, a data processing method, an integrated circuit device, and a processor. The matrix multiplier comprises: an LDS configured to store a first matrix according to a row sequence; K VGPRs configured to store columns in a second matrix, each VGPR storing one column of the second matrix; and K VSPs connected to the K VGPRs in a one-to-one correspondence manner, wherein the LDS is connected to each VSP by means of a bus, so that elements in the first matrix are parallelly loaded to the K VSPs one by one, and are multiplied by elements corresponding to the columns respectively stored in the K VGPRs; the K VSPs parallelly sequentially accumulate multiplication results generated by the elements in the saw row of the first matrix and corresponding elements of the second matrix one by one to obtain all elements in the same row of a third matrix, thereby completing multiplication of the first matrix and the second matrix. The matrix multiplier can perform parallel computation on all the elements in the same row of the third matrix, so that the number of times of obtaining the elements from the first matrix is reduced.
Inventors:
ZUO HANG (CN)
Application Number:
PCT/CN2020/114000
Publication Date:
June 24, 2021
Filing Date:
September 08, 2020
Export Citation:
Assignee:
CHENGDU HAIGUANG MICROELECTRONICS TECH CO LTD (CN)
International Classes:
G06F17/16
Foreign References:
| CN111079081A | 2020-04-28 | |||
| CN109992743A | 2019-07-09 | |||
| CN104238993A | 2014-12-24 | |||
| CN102375721A | 2012-03-14 | |||
| US5784636A | 1998-07-21 |
Attorney, Agent or Firm:
CHOFN INTELLECTUAL PROPERTY (CN)
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