Technical Field

[0001] The present disclosure relates to circuitry and methods for measuring impedance.

Background

[0002] Impedance sensors are used in many applications to monitor and/or detect changes in a variable which affects impedance. An example application is in electrochemical sensing, where electrochemical sensors are widely used for the detection of one or more particular chemical species, analytes, as an oxidation or reduction current. Such sensors comprise an electrochemical cell, consisting of two or more electrodes configured for contact with an analyte whose concentration is to be ascertained. Such sensors also comprise circuitry for driving one or more of the electrodes and for measuring a response at one or more of the electrodes.

[0003] Conventional drive and measurement circuitry for detecting impedance and changes therein, typically comprises several amplifiers, feedback and/or feedback loops in addition to other processing circuitry, such as analog-to-digital converters (ADCs). Such circuitry can take up a large amount of space on-chip, as well as being relatively process intensive, thereby utilising large amounts of power. When such measurement circuitry is battery powered, it is desirable for such circuitry to be as small as possible and use as little power as possible.

Summary

[0004] According to a first aspect of the disclosure, there is provided measurement circuitry comprising: a first half bridge, comprising: a first impedance coupled between an input voltage node for receiving an input voltage and a first node; and a second impedance coupled between the first node and a reference voltage node, the first impedance or the second impedance comprising a first voltage-controlled oscillator (VCO) having a first input coupled to the first node and a first output for outputting a first oscillating signal having a first frequency proportional to the current flowing in the half bridge.

[0005] The measurement circuitry may further comprise: a first counter, comprising: a data input for receiving the first output; a clock input for receiving a clock signal; and a counter output, the data input clocked by the clock input.

[0006] In a first mode, the first frequency may be faster than a clock frequency of the clock signal, and the counter may be incremented by successive oscillations of the first oscillating signal and reset by the clock signal. In a second mode, the clock frequency may be faster than the first frequency, and the counter may be incremented by the successive oscillations of the clock signal and reset by the first oscillating signal.

[0007] The measurement circuitry may further comprise: a second half bridge, comprising: a third impedance coupled between the input voltage node and a second node; and a fourth impedance coupled between the second node and the reference voltage node. The third impedance or the fourth impedance may comprise a second voltage-controlled oscillator (VCO) having a second input coupled to the second node and a second output for outputting a second oscillating signal having a second frequency.

[0008] The third impedance may comprise a second electrochemical cell.

[0009] The measurement circuitry may further comprise: a difference module configured to: receive the first and second oscillating signals; and generate a difference signal proportional to the difference between the first and second frequencies.

[0010] The difference module may comprise: a first counter having a first data input for receiving the first oscillating signal and a first clock input for receiving a clock signal, the first counter configured to generate a first count signal; a second counter having a second data input for receiving the second oscillating signal and a second clock input for receiving the clock signal, the second counter configured to generate a second count signal; and a subtraction module configured to subtract one from the other to generate the difference signal. [0011 ] A gain compensation module may be provided. The gain compensation module may comprise: an adder configured to combine the first and second count signals to generate a common mode signal; and a gain compensation module configured to normalise a gain, k, in the difference signal associated with the first and second VCOs using the common mode signal.

[0012] The gain, k, may be defined as:

₇ ^ 2V ^v i-n - ^J Scm k = -

2Z ₀ *

[0013] where Vin is the input voltage, Scm is the common mode voltage, and Z0 is the value of the first impedance or the third impedance.

[0014] The measurement circuitry may further comprise: a first linearisation module configured to linearise the first count signal provided to the subtraction module based on the input voltage and a first gain, k1 , of the first VCO; and a second linearisation module configured to linearise the first count signal provided to the subtraction module based on the input voltage and a second gain, k2, of the first VCO.

[0015] The measurement circuitry may further comprise: a counter, comprising: a data input configured to receive the first oscillating signal; and a clock input configured to receive the second oscillating signal, wherein the data input is clocked by the clock input.

[0016] The measurement circuitry may further comprise: a frequency divider, the frequency divider configured to frequency divide the first oscillating signal to be provided at the data input or the second oscillating signal to be provided to the clock input.

[0017] The first and second potential dividers may be arranged as an unbalanced bridge.

[0018] The measurement circuitry may be configured to operate in a low-power mode in which a plurality of MOSFETs of the first VCO are configured to operate in a subthreshold region. [0019] During operating in the subthreshold mode, the plurality of MOSFETs may comprise at least one NMOS device having a bulk and a drain connected to one another. Additionally or alternatively, at least one NMOS device may have a bulk and a gate connected to one another. Additionally or alternatively, at least one NMOS device may have a bulk connected to a supply voltage.

[0020] During operating in the subthreshold mode, the plurality of MOSFETs may comprise at least one PMOS device having a bulk and a drain are connected to one another. Additionally or alternatively, at least one NMOS device may have a bulk and a gate connected to one another. Additionally or alternatively, at least one NMOS device may have a bulk connected to reference voltage, e.g. ground (GND).

[0021 ] The first VCO may comprises a ring oscillator.

[0022] The first impedance may comprise a first electrochemical cell.

[0023] The first electrochemical cell may comprise a counter electrode coupled to the input voltage node; and a working electrode coupled to the first node. The first electrochemical cell may further comprise a reference electrode coupled to the input voltage node. The first electrochemical cell may comprise a second counter electrode and/or a second working electrode.

[0024] The first electrochemical cell may comprise a counter electrode coupled to the reference voltage node; and a working electrode coupled to the first node. The first electrochemical cell may further comprise a reference electrode coupled to the reference voltage node. The first electrochemical cell may comprise a second counter electrode and/or a second working electrode.

[0025] The electrochemical cell may be configured to sense one or more analytes. The analytes may be selected from a list comprising glucose, one or more lactates, and one or more ketones.

[0026] According to another aspect of the disclosure, there is provided a continuous glucose monitor comprising the measurement circuitry described above. [0027] According to another aspect of the disclosure, there is provided a device comprising the measurement circuitry described above and/or the continuous glucose monitor. The device may comprise one of a mobile computing device, a laptop computer, a tablet computer, a games console, a remote control device, a home automation controller or a domestic appliance, a toy, a robot, an audio player, a video player, or a mobile telephone, and a smartphone.

[0028] Throughout this specification the word "comprise", or variations such as "comprises" or "comprising", will be understood to imply the inclusion of a stated element, integer or step, or group of elements, integers or steps, but not the exclusion of any other element, integer or step, or group of elements, integers or steps.

Brief Description of Drawings

[0029] Embodiments of the present disclosure will now be described by way of nonlimiting examples with reference to the drawings, in which:

[0030] Figure 1 is a schematic diagram of a state-of-the-art measurement circuit;

[0031] Figure 2 is a schematic diagram of a state-of-the-art voltage-controlled ring oscillator;

[0032] Figure 3 is a schematic diagram of a measurement circuit in accordance with embodiments of the present disclosure;

[0033] Figure 4 is an equivalent circuit of the measurement circuit shown in Figure 3;

[0034] Figure 5 is a load line plot for the measurement circuit shown in Figure 3;

[0035] Figure 6 is a schematic diagram of a measurement circuit in accordance with embodiments of the present disclosure;

[0036] Figures 7 to 9 are schematic diagrams of example implementations of a difference module such as that shown in Figure 6; [0037] Figure 10 is a schematic diagram of a measurement circuit in accordance with embodiments of the present disclosure;

[0038] Figure 11 is a schematic diagram of a measurement circuit in accordance with embodiments of the present disclosure;

[0039] Figure 12 illustrates an example implementation of the measurement circuit of Figure 3 as an analyte sensor;

[0040] Figure 13 illustrates an example implementation of the measurement circuit of Figure 6 as an analyte sensor;

[0041 ] Figure 14 illustrates a measurement circuit for an electrochemical cell according to embodiments of the present disclosure;

[0042] Figure 15 illustrates a measurement circuit for an electrochemical cell according to embodiments of the present disclosure;

[0043] Figure 16 illustrates a measurement circuit for an electrochemical cell according to embodiments of the present disclosure;

[0044] Figure 17 illustrates a dynamic switching regime for the measurement circuit of Figure 6;

[0045] Figure 18 illustrates an example implementation of the voltage-controlled ring oscillator shown in Figure 2;

[0046] Figures 19 and 20 illustrate variations of bulk biasing for an inverter of the ring oscillator shown in Figure 18;

[0047] Figure 20 illustrates a measurement circuit comprising an electrochemical cell comprising multiple working electrodes; and

[0048] Figure 21 illustrates a measurement circuit comprising an electrochemical cell comprising multiple counter electrodes. Description of Embodiments

[0049] Figure 1 is schematic diagram of a known voltage divider circuit 100. The circuit 100 comprises a first resistor 102 and a second resistor 104 having respective resistances R1 , R2. The first and second resistors 102, 104 are connected in series between a supply voltage Vdd and a reference node, in this case ground GND. The first and second resistors 102, 104 are connect to each other at a measurement node 106. As is known in the art, the voltage between the reference node GND and the measurement node 106 is dependent on ratio of the resistances R1 , R2 of the first and second resistors 102, 104. An input of an analog-to-digital converter (ADC) 108 is connected to the measurement node 106 to convert the voltage at the measurement node 106 to a digital representation Sout which can then be processed by a digital signal processor (DSP) or other digital device. To function, the ADC 108 requires power and is thus also coupled to the supply voltage Vdd, although the ADC 108 may alternatively be coupled to a separate supply voltage (not shown). The voltage divider circuit 100 shown in Figure 1 comprising the first and second resistors 102, 104 is also known in the art as a half bridge or a potential divider.

[0050] The circuit 100 shown in Figure 1 is commonly used in the art to measure changes in impedance. In such applications, the first and/or second resistors 102, 104 are replaced with elements under test having an impedance which varies with variations in some internal or external condition. A disadvantage of the circuit 100 when used in combination with a digital system is that a constant supply voltage Vdd needs to be provided the resistor pair 102, 104 as well as to the ADC 108. When used as for measurement in battery operated systems, this can lead to excessive use of power.

[0051] Embodiments of the present disclosure aim to address or at least ameliorate one or more of the above problems by replacing the ADC 108 and the second resistor 104 with a voltage-controlled oscillator (VCO).

[0052] Figure 2 is schematic diagram of a voltage-controlled oscillator (VCO) 200 comprising an odd number of N inverters 2-1 , 2-2, 2-N connected in series. The output of the Nth inverter 2-N is coupled to the input of the first inverter 2-1 in the string as well as the output of the VCO 200. Since each inverter computes the logical NOT of its input, the output of the Nth inverter 2-N is the logical NOT of the input to the first inverter 2-1 . Each of the inverters 2-1 , 2-2, 2-N imparts a delay on the input signal which is compounded at the output of the Nth inverter. Due to this combined delay, the feedback of the output of the Nth inverter 2-N to the input of the first inverter 2-1 causes oscillation in the output signal Sout. The delay associated with each of the inverters 2-1 , 2-2, 2-N is dependent on the supply voltage Vdd. Thus, as the supply voltage Vdd varies, so too does the frequency of oscillation of the VCO 200.

[0053] Thus, the oscillating output of the VCO 200 is a digital representation of the voltage Vdd. Thus, the output signal Sout can be used to determine the level of the supply voltage Vdd.

[0054] Figure 3 is a schematic diagram of a measurement circuit 300 according to embodiments of the present disclosure. The measurement circuit 300 is in the form of a half bridge comprising an impedance Z (such as an impedance under test) coupled in series with a VCO 302, such as the VCO 200 shown in Figure 2. The impedance Z is coupled between a supply voltage Vdd and a measurement node 304. The VCO 302 is coupled between the measurement node 304 and a reference voltage, in this case ground GND (nominally zero volts). Thus, the VCO 302 generates an oscillating output signal, the frequency of which is proportional to the voltage VL across the VCO 302 and thus the voltage at the measurement node 304. Variations in the impedance Z lead to variations in the voltage drop across the impedance Z and thus the voltage drop VL across the VCO 302.

[0055] To decode the output signal from the VCO 302, the measurement circuit 300 may further comprise a counter 306 having a data input for receiving the output signal from the VCO 302 and a clock input for receiving a clock signal Fs. The counter 306 generates a decoded output signal Sout based on the output of the VCO 302.

[0056] The measurement circuit 300 may operate in two modes. In a first mode, the frequency of oscillation of the VCO 302 is faster than the frequency of the reference clock Fs. In which case, the counter 306 is incremented by successive oscillations of the VCO 302 and reset by the reference clock Fs. In this mode, the frequency of oscillation of the VCO 302 is proportional to the value of the count of the counter 306 between resets by the reference clock Fs. The first mode is a typical mode of operation and the following explanation with reference to Figures 4 and 5 represent this first mode of operation. In a second mode, the reference clock Fs is faster than the frequency of the VCO 302. In this second mode, the counter 306 is incremented by the reference clock Fs and reset by the VCO 302. In other words, the output from the VCO 302 is provided as the clock signal for the counter 306 and the reference clock Fs is provided as the data/counter input. In this mode, the output Sout represents the frequency of the reference clock Fs divided by the frequency of the VCO 302. Such a mode would have the effect of inverting equations shown below with reference to Figures 4 and 5. Operation in the second mode may in some circumstances lead to computational savings in the processing of the counter output signal Sout. In some embodiments, the circuit 300 may comprise switching circuitry configured to switch the connections of the VCO 302 output and the reference clock Fs between the data and clock inputs of the counter 306.

[0057] Figure 4 is a schematic diagram of an equivalent circuit 400 to the measurement circuit 300 shown in Figure 3. The VCO 302 can be modelled as a voltage controlled non-linear current source cp. It will be appreciated that the current source cp may take various forms depending on the characteristics of the VCO 302. In the following nonlimiting example, a parabolic form is described, for illustrative purposes only. The voltage controlled non-linearity is in the form: W = kV _L ²

[0058] Where VL is the voltage drop across the non-linear current source q>.

[0059] A load line plot can thus be drawn as shown in Figure 5. The stable operating point 502 is shown in Figure 5 where the load line intersects the current vs voltage curve for the VCO 302. From this, an equation for Vdd can be derived as shown below.

Vdd = Z(p(y _L ) + V _L

[0060] This gives rise to the following quadratic equation which can be solved to find V _L , which is the voltage drop across the VCO 302. 0 = kZV + V _L - Vdd

[0061] The voltage V _L across the VCO 302 is given by the solution to the above equation.

[0062] Figure 6 is a schematic diagram of another measurement circuit 600. The measurement circuit 600 comprises a modified Wheatstone full bridge in which two resistors have each been replaced with voltage-controlled oscillator. Specifically, the measurement circuit 600 comprises a first impedance Zn, a second impedance Zp, a first VCO 602 and a second VCO 604. The first impedance Zn is coupled between a supply voltage Vdd and the first VCO 602, for example to a supply rail of the first VCO 602. The first VCO 602 is also coupled to a reference node, in this example ground GND. The second impedance Zp is coupled between a supply voltage Vdd and the second VCO 604, for example to a supply rail of the second VCO 604. The second VCO 604 is also coupled to the reference node. Like the half bridge circuit 300 shown in Figure 3, as the impedances Zn, Zp change, the voltage drop across each of those impedances Zn, Zp also change. In turn, the voltage drop across each of the first and second VCOs 602, 604 changes thereby changing the frequency of oscillation of respective output signals Fn, Fp from the first and second VCOs 602, 604.

[0063] The measurement circuit 600 further comprises a difference module 606 configured to output a signal Sout representing the difference in frequency of the first and second output signals Fn, Fp generated by the first and second VCOs 602, 604.

[0064] Thus, the output signal Sout is a digital signal which varies in dependence on the first and second impedances Zn, Zp. Specifically, under the condition that k*Z < 1 (where k is the gain associated with each of the first and second VCOs 602, 604 and Z is the impedance of each of the first and second VCOs 602, 604), the output signal Sout may be defined by the following equation.

Sout = k(Z _N - ZpWh

[0065] . Hence, any change in the impedances Zn or Zp may be detected. [0066] It will be appreciated that in practice, the gain k of each of the first and second VCOs 602, 604 may differ slightly due to analog mismatch and/or device variation between the first and second VCOs 602, 604. Embodiments of the present disclosure may take into account such variation by testing the circuit 600 during a calibration phase. It will also be appreciated that the gain k is a function of the region of operation of transistors (e.g. MOSFETs) in the first and second VCOs 602, 604. As will be described in more detail below, depending on the mode of operation of the measurement circuit 600, MOSFETs of the first and second VCOs 602, 604 may be operated in any suitable mode, e.g. a strongly or fully saturated mode or a sub-threshold mode. The value of the gain k will be different when operating in each of these modes. These differences may be taken into account when processing the output signal Sout.

[0067] The measurement circuit 600 shown in Figure 6 may be operated in two different modes - a balanced mode or an unbalanced mode. In the unbalanced mode, the first impedance Zn is a fixed reference impedance and the second impedance Zp is the impedance under test. The modified Wheatstone bridge is therefore unbalanced. In the balanced mode, the first and second impedances Zn, Zp are both impedance under test and configured such that a change in an external condition causes the first impedance Zn to vary in a substantially equal and opposite way to the second impedance Zp. The relationship between Zp, Zn and Sout in the balanced and unbalanced modes is summarised in the following table.

[0068] It can be seen that by operating the measurement circuit 600 in the balanced mode, the variation in output signal Sout is double that when operating the measurement circuit 600 in the unbalanced mode.

[0069] Figure 7A shows an example implementation of the difference module 606. The difference module comprises a first counter 702, a second counter 704 and a subtraction module 706. The first counter 702 has a data input configured to receive the output signal Fn from the first VCO 602. The second counter 704 has a data input configured to receive the output signal from the second VCO 604. The first and second counters 702, 704 each have a clock input configured to receive a common clock signal Fs. First and second count signals output from the first and second counters 702, 704 are provided to the subtraction module 706 which is configured to subtract the second count signal from the first count signal to generate the output signal Sout. In other embodiments, the subtraction module 706 may subtract the first count signal from the second count signal to generate the output signal Sout.

[0070] Like the counter 306 of the measurement circuit 300, the counters 702, 704 may be operated in two different modes, depending on whether frequencies of respective first and second VCOs 602, 604 are higher or lower than the frequency of the common clock signal Fs. Referring to the first VCO 602 as an example, in a first mode where the frequency of the first output signal Fn is higher than that of the clock signal Fs, the first output signal Fn is provide as the data/counter input to the counter 702 and the clock signal Fs is provided as a clock input to the counter 702. In a second mode where the frequency of the first output signal Fn is lower than that of the clock signal Fs, the clock signal Fs is provide as the data/counter input to the counter 702 and the first output signal Fn is provided as a clock input to the counter 702. The second VCO 604, second output signal Fp and the second counter 704 may be operated in a similar manner (in a first or second mode depending on the relative frequency of the second VCO 604 vs the common clock signal Fs).

[0071] Figure 7B shows another example implementation of the difference module 606. The difference module 606 in this embodiment comprises a counter 707 and an (optional) divider 708. The counter 707 has a data input and a clock input.

[0072] The first VCO output signal Fn from the first VCO 602 is provided to the clock input of counter 707. The second VCO output signal Fp from the second VCO 604 is provided to the data input of the counter 707. As such, the first VCO output signal Fn is configured to clock the counter 707. By clocking one of the oscillating output signals Fn, Fp by the other of the output signals Fn, Fp the output Sout from the counter 707 represents a ratio of the two clocks, i.e.:

[0073] The frequency divider 708 is optionally provided to divide the frequency output from the first VCO 602 by a denominator M, thereby increasing the frequency ratio between the first and second VCO output signals Fn, Fp. Optionally, instead of or in addition to providing the frequency divider 708, the sensitivity of the first VCO 602 may be reduced (or the sensitivity of the second VCO 602 adjusted/increased). For example, the gain k of the first VCO 602 may be reduced such that a higher voltage is needed to operate the first VCO 602 at the same frequency, thereby reducing the sensitivity of the first VCO 602.

[0074] In a variation of the embodiment shown in Figure 7B, instead of dividing the output signal Fn from the first VCO 602, a frequency divider may be provided between the second VCO 604 and the counter 707 to divide down the second output signal Fp. In other words, the inputs to the difference module 606 may be switched. The implementation shown in Figure 7B has a comparably lower power consumption when compared to the implementation shown in Figure 7A due to the provision of fewer components.

[0075] Figure 8 schematically illustrates a difference module 800 which is a variation of the difference module 606 shown in Figure 7. In this example, the difference module 800 is configured to determine a difference signal and a common mode signal from the first and second count signals. Using these signals, the gain k associated with the measurement circuit 600 can be determined and the output signal compensated to take into account such gain k.

[0076] The difference module 800 comprises a first counter 802, a second counter 804, a subtraction module 806, an adder 808 and a gain compensation module 810. The first counter 802 has a data input configured to receive the output signal Fn from the first VCO 602. The second counter 804 has a data input configured to receive the output signal from the second VCO 604. The first and second counters 802, 804 each have a clock input configured to receive a common clock signal Fs. First and second count signals output from the first and second counters 802, 804 are provided to the subtraction module 806 which is configured to subtract the second count signal from the first count signal to generate a difference signal Sdiff. The first and second count signals are also provided to the adder 808 which is configured to combine the first and second count signals to form a common mode signal Scm. The common mode signal Scm and the difference signal Sdiff are provided to the gain compensation module 810. Based on the common mode signal Scm, the gain compensation module 810 is configured to adapt the difference signal Sdiff to compensate for gain associated with the first and second VCOs 602, 604.

[0077] In this configuration, the difference signal Sdiff is given by:

Sdiff = k(Z _N — Zp)V _dd

[0078] The common mode signal Scm is given by:

Scm = V _d {k(Z _N - Z _P )V _dd - 2}

[0079] When operating in the balanced mode (discussed above):

Zp = Zo + AZ Zn = Zo — AZ

[0080] Hence:

Scm = 2V _dd (kZoV _dd - 1)

[0081] Thus, with knowledge of the common mode voltage Scm, the supply voltage Vdd and the reference impedance Zo, it is possible to derive the gain k of the measurement circuit 600. The gain compensation module may then normalise the gain in the difference signal Sdiff and output a gain compensated output signal Sout. [0082] Figure 9 schematically illustrates a difference module 900 which is a variation of the difference module 606 shown in Figure 7. As noted above, the current flow through each VCO 602, 604 as exemplified in the graphical illustration of Figure 5. The difference module 900 may be configured to correct for such non-linearity in signals output from the VCOs 602, 604.

[0083] The difference module 900 comprises first and second counters 902, 904, first and second linearisation modules 906, 908 and a subtraction module 910. The first counter 902 has a data input configured to receive the output signal Fn from the first VCO 602. The second counter 904 has a data input configured to receive the output signal from the second VCO 604. The first and second counters 902, 904 each have a clock input configured to receive a common clock signal Fs. First and second count signals Sn, Sp are respectively provided to the first and second linearisation modules 906, 908 which are each configured to linearise the first and second count signals Sn, Sp respectively. Each linearisation module 906, 908 may be configured to perform the following function on respective first and second count signals Sn, Sp. The term “S” has been used as a generalisation of “Sn” and “Sp”. This equation was linearised using a Pade approximant.

[0084] It will be appreciated that both the supply voltage Vdd and the gain k need to be known to generate the first and second linearised signals S’n, S’p. The supply voltage Vdd can either be measured or known in advance. The gain k may be calculated, for example, using the method described above with reference to Figure 8. Alternatively, the gain k may be estimated or determined through calibration.

[0085] The first sand second linearised count signals S’n, S’p are then provided to the subtraction module 910 which is configured to subtract the first linearised count signal S’n from the second linearised count signal S’p (or vice versa) and generate a linearised output signal Sout.

[0086] It will be appreciated that one or more elements of the difference module 800 may be combined with one or more elements of the difference module 900 to provide both gain compensation and linearisation. For example, the linearisation modules 906, 908 of the difference module 900 may be provided directly after the first and second counters 802, 804 of the difference module 800 so that the signal provided to the subtraction module 806 and the adder 808 are adjusted to remove or ameliorate nonlinearities.

[0087] In embodiments described above, various counters 702, 704, 802, 804, 902, 904 are clocked with an external clock signal Fs. In some embodiment, however, it may be advantageous not to require an external frequency reference (e.g. clock signal Fs).

[0088] Figure 10 is a schematic diagram of a measurement circuit 1000 which is a variation of the measurement circuit 600 shown in Figure 6, where like parts have been given like numerals. In the measurement circuit 1000, one half of a modified Wheatstone bridge is used to generate a frequency reference. Like the measurement circuit 600, the measurement circuit 1000 comprises the first and second VCOs 602, 604, the first and second impedances Zn, Zp. Additionally, the measurement circuit 1000 comprises a counter 1002 and optionally a frequency divider 1004. The counter 1002 has a data input and a clock input.

[0089] In this embodiment, the first impedance Zn is a fixed reference impedance and the second impedance Zp is an impedance under test. The first VCO output signal Fn from the first VCO 602 is provided to the clock input of counter 1002. The second VCO output signal Fp from the second VCO 602 is provided to the data input of the counter 1002. As such, the first VCO output signal Fn is configured to clock the counter 1002. By clocking one of the oscillating output signals Fn, Fp by the other of the output signals Fn, Fp the output Sout from the counter 1002 represents a ratio of the two clocks, i.e.:

[0090] The frequency divider 1004 is optionally provided to divide the frequency output from the first VCO 602 by a denominator M, thereby increasing the frequency ratio between the first and second VCO output signals Fn, Fp. Optionally, instead of or in addition to the frequency divider 1004, the sensitivity of the first VCO 602 may be reduced. For example, the gain k of the first VCO 602 may be reduced such that a higher voltage is needed to operate the first VCO 602 at the same frequency, thereby reducing the sensitivity of the first VCO 602.

[0091] In a variation of the embodiment shown in Figure 10, instead of dividing the output signal Fn from the first VCO 602, a frequency divider may be provided between the second VCO 604 and the counter 1002 to divide down the second output signal Fp.

[0092] Figure 11 is a schematic diagram of a measurement circuit 1100 which is a skew variant of the measurement circuit 600 shown in Figure 6. In contrast to the measurement circuit 600 of Figure 6, the first VCO 602 is coupled between the supply voltage Vdd and the first impedance Zn, and the first impedance Zn is coupled between the reference node GND and the first VCO 602. The measurement circuit 1100, operating as a skew bridge, may result in a more stable common mode signal Scm, which in turn may make it easier to estimate the effective gain k of the conversion process.

[0093] As mentioned above, the measurement circuits 300, 600, 1000, 1100 may be used to measure changes in impedance of one or more circuit elements provided therein. Figures 12, 13A and 13B provide three examples of the use of measurement circuits described herein for the measurement of changes in impedance of electrochemical cells. As is known in the art, electrochemical cells can be used to measure concentrations of analytes (such as glucose) present at electrodes of such cells. Generally, electrochemical cells consist of two or more electrodes configured for contact with an analyte whose concentration is to be ascertained. Such sensors may also comprise circuitry for driving one or more of the electrodes and for measuring a response at one or more of the electrodes. Changes in concentration of an analyte lead to changes in the impedance characteristics of such cells, which can be measured by the various measurement circuits described herein.

[0094] Figure 12 is a schematic illustration of the measurement circuit 300, the impedance Z comprising an electrochemical cell 1202. Changes in impedance Z of the electrochemical cell 1202 will lead to a change in the output signal Sout from the counter 306. [0095] Figure 13A is a schematic illustration of the measurement circuit 600, the second impedance Zp comprises a two-electrode electrochemical cell 1302A. Changes in the impedance Zp of the electrochemical cell 1302A are translated into changes in the output signal Sout from the difference module 606.

[0096] Figure 13B is a schematic illustration of the measurement circuit 600, the second impedance Zp comprises a three-electrode electrochemical cell 1302B. The three-electrode cell 1302B comprises a working electrode WE, a counter electrode CE and a reference electrode RE. The counter electrode CE and the working electrode WE are coupled to the supply voltage Vdd. The working electrode WE is coupled to the second VCO 604. Changes in the impedance Zp of the electrochemical cell 1302B are translated into changes in the output signal Sout from the difference module 606.

[0097] Figure 14 is a schematic illustration of a measurement circuit 1400 which is a variation of the measurement circuit 300 of Figure 3, specifically for use with an electrochemical cell 1402. Like parts have been given like numberings. The electrochemical cell comprises three electrodes, namely a counter electrode CE, a working electrode WE and a reference electrode RE. In addition to the VCO 302 and the counter 306, the circuit 1400 comprises a first comparator 1404 and a second comparator 1406. First and second (e.g. inverting and non-inverting) inputs of the first comparator 1404 are coupled to the reference electrode RE and the working electrode WE respectively. An output of the first comparator 1404 is coupled to a first (inverting) input of the second comparator 1406. A bias voltage Vbias is provided to the second (non-inverting) input of the second comparator 1406 whose output is provided to the counter electrode CD.

[0098] To determine a characteristic of the electrochemical cell 1402, and therefore an analyte concentration, a measurement current is injected by the second comparator 1406 at the counter electrode CE and a current at the working electrode WE is measured. The current flow through the VCO 302 is proportional to this current at the working electrode WE. The reference electrode RE is used to measure a voltage drop between the working electrode WE and the reference electrode RE. This voltage drop is measured by the first comparator 1404 which provides the result (i.e. the difference in voltage between the working and reference electrodes WE, RE) to the second comparator 1406. The second comparator 1 06 then adjusts the voltage at the counter electrode CD to keep the voltage drop between the working electrode WE and the reference electrode RE constant. As the resistance in the cell 1402 increases, the voltage drop measured at the reference electrode increases. In response, the measurement current injected at the counter electrode CE is decreased. Likewise, as the resistance in the cell 1402 decreases, the voltage drop measured at the reference electrode decreases. In response, the measurement current injected at the counter electrode CE is increased. Thus the electrochemical cell 1402 reaches a state of equilibrium where the voltage drop between the reference electrode RE and the working electrode WE is maintained constant.

[0099] Figure 15 is a schematic illustration of a measurement circuit 1500 which is a variation of the measurement circuit 600 of Figure 3, specifically for use with an electrochemical cell 1502. Like parts have been given like numberings. The electrochemical cell comprises three electrodes, namely a counter electrode CE, a working electrode WE and a reference electrode RE. In addition to the first and second VCOs 602, 604 and the difference module 606, the circuit 1500 comprises a first comparator 1504 and a second comparator 1506. First and second (e.g. inverting and non-inverting) inputs of the first comparator 1504 are coupled to the reference electrode RE and the working electrode WE respectively. An output of the first comparator 1504 is coupled to a first (inverting) input of the second comparator 1506. A bias voltage Vbias is provided to the second (non-inverting) input of the second comparator 1506 whose output is provided to the counter electrode CD. The first VCO 602 is coupled between the reference voltage (e.g. ground (GND)) and the output of the first comparator 1504.

[0100] To determine a characteristic of the electrochemical cell 1502, and therefore an analyte concentration, a measurement current is injected by the second comparator 1506 at the counter electrode CE and a current at the working electrode WE is measured by the second VCO 302 (the current flow through the VCO 302 is proportional to this current at the working electrode WE). The reference electrode RE is used to measure a voltage drop between the working electrode WE and the reference electrode RE. This voltage drop is measured by the first comparator 1404 which provides the result (i.e. the difference in voltage between the working and reference electrodes WE, RE) to the second comparator 1406 and also to the supply rail of the first VCO 602. The second comparator 1406 then adjusts the voltage at the counter electrode CD to keep the voltage drop between the working electrode WE and the reference electrode RE constant. As the resistance in the cell 1402 increases, the voltage drop measured at the reference electrode increases. In response, the frequency of oscillation of the first VCO 602 increases and the measurement current injected at the counter electrode CE is decreased. Likewise, as the resistance in the cell 1402 decreases, the voltage drop measured at the reference electrode decreases. In response, the frequency of oscillation of the first VCO 602 decreases and the measurement current injected at the counter electrode CE is increased. Thus the electrochemical cell 1402 reaches a state of equilibrium where the voltage drop between the reference electrode RE and the working electrode WE is maintained constant.

[0101] Figure 16 shows a measurement circuit 1600 which is a variation the circuit 1500 shown in Figure 15, like parts having been given like numerals. The measurement circuit 1600 differs from that in Figure 15 in that the first VCO 602 is coupled between the reference voltage (e.g. ground (GND)) and the second (non-inverting) input of the first comparator 1504 (rather than the output of the first comparator 1504). Like in the measurement circuit 1500 of Figure 15, the frequency oscillation of the first VCO 602 is dependent on the voltage at the reference electrode RE.

[0102] The electrochemical cells 1202, 1302A, 1302B, 1402, 1502 may be engineered to monitor for one or more analytes. Such analytes may include one or more of ketones, oxygen, lactate and glucose.

[0103] As mentioned above with reference to the measurement circuit 600 of Figure 6, there may be some mismatch between left and right half bridges (e.g. the left and right VCOs 602, 604) of the measurement circuit 600. To account for such mismatch, in some embodiments the first and second VCOs 602, 604 may be rotated between the first and second impedances Zn, Zp. In doing so, the effective gain k of each of side of the bridge is equal to the average of the gain k of the two VCOs 602, 604.

[0104] Figure 17 illustrates example switching circuitry 1700 for rotating connection of the VCOs 602, 604 between the first and second impedances Zn, Zp. The switching circuitry comprises a first switch S1 coupled between the first impedance Zn and the first VCO 602, a second switch S2 coupled between the first impedance Zn and the second VCO 604, a third switch S2 coupled between the second impedance Zp and the first VCO 602, and a fourth switch coupled between the second impedance Zp and the second VCO 604. The switches S1 :S4 are controlled such that, during a first phase, the first and second VCOs 602, 604 are connected respectively to the first and second impedances Zn, Zp and, during a second phase, the first VCO 602 is connected to the second impedance Zp and the second VCO 604 is connected to the first impedance Zn. It will be appreciated that one or more elements of the switching circuitry 1700 shown in Figure 17 could equally be used for rotating connection of VCOs in any one of the measurement circuits 600, 1000, 1100, 1300, 1500, 1600 described above.

[0105] It will be appreciated that voltage-controlled oscillators such as the ring oscillator 200 shown in Figure 2, are typically implemented with MOSFET semiconductor topology. MOSFETs can be biased to operate in a plurality of different modes. A conventional mode of operation for implementing VCOs is the fully saturated mode where both VGS > VT and VDS > VGS-VT, where VGS is the gate-source voltage, VT is the threshold, and VDS is the drain-source voltage of the transistor. However, for low power operations, a subthreshold mode, where VGS < VT, may be used which substantially reduces the power consumption of the MOSFET devices making up the VCO. In this mode of operation, the current for low VDS is approximately given by:

<p(V) = / ₀ — e' ^nV r ' Lt

Where:

/ ₀ = 10 ^-9 n = 1.4 kT

V _T = — = 26mV

¹ 9

[0106] Figure 18 illustrates a novel implementation of the VCO 200 of Figure 2 for operation in a subthreshold mode. In contrast, in Figure 18, each of the inverters 2-1 , 2-2, 2-N comprises a p-type MOSFET 1 P, 2P, NP and an n-type MOSFET 1 N, 2N, NN. In a conventional inverter implementations, respective MOSFET bulks are connected to their sources. In contrast to convention, bulks of the p-type MOSFETs 1 P, 2P, NP are coupled to respective drains of the p-type MOSFETs 1 P, 2P, NP. Additionally, again in contrast to convention, bulks of the n-type MOSFETs 1 N, 2N, NN are coupled to respective drains of the n-type MOSFETs 1 N, 2N, NN. Pulling the bulk of the n-type devices high and the p-type devices low when operating in the subthreshold mode results in a reduction in threshold voltage VT for teach of the devices.

[0107] Figures 19 and 20 two variations for a single inverter 2-N which may be repeated for all inverters in the oscillator shown in Figure 18.

[0108] In Figure 19 a dynamic body biasing variation is shown in which the bulk of each of the MOSFETS NP, NN is coupled to the gate of the inverter 2-N which in turn is driven by a previous inverter in the ring oscillator 200.

[0109] In Figure 20, the bulk of the p-type MOSFET is pulled low, in this case to ground GND and the n-type MOSFET is pulled high, in this case to the supply voltage Vdd.

[0110] In each example shown in Figure 18 to 20, the body effect is used to increase the speed of switching of the ring oscillator 200. Specifically, in each example, it is proposed to pull the voltage at the bulk to a different potential, thereby adjusting the threshold voltage, Vt, of the respective MOSFETs, to either speed up or slow down the VCO 200.

[0111] It will be appreciated that the VCOs described herein may be switchable to operate in a fully saturated mode for higher performance but higher power consumption, and in a subthreshold mode for lower performance but lower power consumption depending on power and performance requirements.

[0112] By reducing the size and power of drive and measurement circuitry, multiple electrochemical sensors may be integrated into a single device, thereby either providing redundancy or enabling the sensing of multiple analytes in a single chip. This may be particularly advantageous in applications such as continuous glucose monitoring, where it may be desirable to measure concentrations of several analytes including but not limited to two or more of glucose, ketones, oxygen, lactate, and the like.

[0113] Figure 21 is a schematic illustration of a multi-analyte measurement circuit 2100 which is a variation of the measurement circuit 300 shown in Figure 12. The measurement circuit 2100 comprises a measurement cell 2102 comprising first and second working electrodes WE1 , WE2 and a common counter electrode CE1. The circuit 2100 further comprises first and second VCOs 2104, 2106 and first and second counters 2108, 2110. The counter electrode is coupled to a supply voltage Vdd. The first working electrode WE1 is coupled to a power supply node of the first VCO 2104. The second working electrode WE2 is coupled to a power supply node of the second VCO 2106. The first and second VCOs 2104, 2106 are also coupled to a reference voltage (in this case ground GND). Oscillating outputs of the first and second VCOs 2104, 2106 are provided to the respective first and second counters 2108, 2110. Thus, the first VCO 2104 and the first counter 2108 are configured in a similar manner to the VCO 302 and counter 306 of the circuit 300 shown in Figure 12. Likewise, the second VCO 2106 and the second counter 2110 are configured in a similar manner to the VCO 302 and counter 306 of the circuit 300 shown in Figure 12. Thus, the measurement circuit 2100 is able to measure two different analyte concentrations using a common measurement cell 2102.

[0114] Figure 22 is a schematic illustration of a multi-analyte measurement circuit 2200 which is a variation of the measurement circuit 2100 shown in Figure 21 , like parts having like reference numerals. Instead of the measurement cell 2102 comprising two working electrodes WE1 , WE2 and a single counter electrode CE, the measurement circuit 2200 comprises a measurement cell 2202 comprising first and second counter electrodes CE1 , CE2 and a common working electrode WE. The first counter electrode CE1 is coupled to a power supply node of the first VCO 2104. The second counter electrode CE2 is coupled to a power supply node of the second VCO 2106. The first and second VCOs 2104, 2106 are also coupled to a reference voltage (in this case ground GND). Oscillating outputs of the first and second VCOs 2104, 2106 are provided to the respective first and second counters 2108, 2110. Thus, like the measurement circuit 2100, the measurement circuit 2200 is able to measure two different analyte concentrations using a common measurement cell 2202. [0115] The various circuitry and electrochemical cells described herein may be incorporated into a continuous analyte sensor or a continuous glucose sensor or a continuous glucose monitor. The terms “continuous analyte sensor”, “continuous glucose sensor”, and “continuous glucose monitor” as used herein, will be well-known to a person of ordinary skill in the art and are not to be limited to a special or customized meaning. These terms refer, without limitation, to a device that continuously measures a concentration of an analyte/glucose and/or calibrates the sensor or an electrochemical cell incorporated therein (e.g., by continuously adjusting or determining the sensor's sensitivity and background).

[0116] As mentioned previously, the power consumption of the various measurement circuits described above is substantially reduced when compared to state-of-the art measurement circuits. Additionally, various embodiments described above are smaller in size and thus take up less circuit real estate. By reducing the size and power of drive and measurement circuitry, the overall performance of such circuitry is improved. This has particular advantages for application in battery operated systems. When sensors are battery powered, for example when used for analyte sensing (e.g. continuous glucose monitoring), it is desirable for such sensors to be as small as possible and use as little power as possible. For analyte monitoring applications, the reduced size and power consumption also means that multiple electrochemical sensors can be integrated into a single device, thereby either providing redundancy or enabling the sensing of multiple analytes in a single chip. This may be particularly advantageous in applications such as continuous glucose monitoring, where it may be desirable to measure concentrations of several analytes including but not limited to two or more of glucose, ketones, oxygen, lactate, and the like.

[0117] The skilled person will recognise that some aspects of the above-described apparatus and methods may be embodied as processor control code, for example on a non-volatile carrier medium such as a disk, CD- or DVD-ROM, programmed memory such as read only memory (Firmware), or on a data carrier such as an optical or electrical signal carrier. For many applications embodiments of the invention will be implemented on a DSP (Digital Signal Processor), ASIC (Application Specific Integrated Circuit) or FPGA (Field Programmable Gate Array). Thus the code may comprise conventional program code or microcode or, for example code for setting up or controlling an ASIC or FPGA. The code may also comprise code for dynamically configuring re-configurable apparatus such as re-programmable logic gate arrays. Similarly the code may comprise code for a hardware description language such as Verilog TM or VHDL (Very high-speed integrated circuit Hardware Description Language). As the skilled person will appreciate, the code may be distributed between a plurality of coupled components in communication with one another. Where appropriate, the embodiments may also be implemented using code running on a field- (re)programmable analogue array or similar device in order to configure analogue hardware.

[0118] Note that as used herein the term module shall be used to refer to a functional unit or block which may be implemented at least partly by dedicated hardware components such as custom defined circuitry and/or at least partly be implemented by one or more software processors or appropriate code running on a suitable general- purpose processor or the like. A module may itself comprise other modules orfunctional units. A module may be provided by multiple components or sub-modules which need not be co-located and could be provided on different integrated circuits and/or running on different processors.

[0119] Embodiments may be implemented in a host device, especially a portable and/or battery powered host device such as a mobile computing device for example a laptop or tablet computer, a games console, a remote-control device, a home automation controller or a domestic appliance including a domestic temperature or lighting control system, a toy, a machine such as a robot, an audio player, a video player, or a mobile telephone for example a smartphone.

[0120] It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. The word “comprising” does not exclude the presence of elements or steps other than those listed in a claim, “a” or “an” does not exclude a plurality, and a single feature or other unit may fulfil the functions of several units recited in the claims. Any reference numerals or labels in the claims shall not be construed so as to limit their scope.