THROUGH A COIL

Field

The present invention relates to the measurement of electrical current. More particularly the invention relates to the measurement of instantaneous current and is suitable for inclusion in a current detector in an electrical energy conversion device.

Background

With the ever increasing desire to improve the efficiency of electric power conversion equipment, every aspect of the process needs to be scrutinised. Conventional electric induction motors are said to consume approximately 70% of all the electricity used in industry and about 45% of all the electricity used globally.

Prior Art

Conventional current measuring devices normally measure current by passing the current through a known medium and measuring some effect that directly relates the amount of charge passed to some other phenomenon.

For example total current flowing through a resistive material, with a known resistivity and at a low temperature coefficient of resistivity, the current is then accurately determined by measuring the voltage drop across the resistive material. A drawback was that power was lost and so efficiency of the measurement device was not ideal.

Another well-known and well used technique is to use the Hall effect where an electric current is created in a conductor exposed to a magnetic field. However, such devices introduce unacceptable times delays and therefore are unable to provide a precise instantaneous indication of current.

In both these cases, there is a requirement to introduce an extra element through which the current to be measured can flow. This introduces, amongst other things, the issues of added cost, complexity, circuit layout problems and resistive losses.

GB 1414985 (Taylor Servomex) teaches an apparatus for developing a signal which represents the value of an input current comprising an integrator, means for applying the current to the integrator and a slope detector is responsive to the output of the integrator to generate an output which is opposite to an unwanted input signal. A disadvantage with the aforementioned apparatus is that, due to its measuring techniques it is only able to provide a delayed value reading.

An aim of the invention is to provide an accurate current measuring device, where the current to be measured does not have to flow through any additional devices or conductors and a reading is provided quickly.

Summary of invention

According to a first aspect of the invention there is provided a circuit for measuring instantaneous current at a point A of a terminal of a coil comprises: a threshold detector which is operative to sense a voltage at A, a slope/rate detector outputs a voltage corresponding to an instantaneous coil current upon detection of a change of the voltage at A; and an integrator measures the voltage at A and outputs a signal which mirrors the current at A.

This circuit uses natural characteristics of the components themselves through which current flows. By understanding what is happening and knowing the circuit impedances, measuring voltages and noting or applying timing, it is possible to calculate the circuit current.

In one preferred embodiment current builds up in a coil with a known inductance (L _a ). Using the equation Exdt=L _a dl and knowing that for a capacitor C _a , ldt=C _a V, the voltage build up across a capacitor C _a is directly equivalent to the current build up in a coil L _a .

At the point the current build up in the coil is terminated, by turning a power switching device off, the voltage across the switching device, with an effective shunt capacitance of C _s , then changes rapidly and this rate of change of voltage also gives the absolute value of current flowing at this point. l=C _s dV/dt. The instant of switch off, or switch on creates a timing point where the opportunity to DC restore waveforms occurs.

This is ideally achieved by clamping the integrator output with the output of the slope rate detector. The circuit and its method of operation have tolerances of the order of the absolute values that are equal to associated components. In practice these are the components through which current flows, so the precision of current measurement is probably of the same order as the precision of the components themselves. In other words if the circuit demands a high precision of components for some reason, then the currents can be calculated quite precisely as well.

Other circuit parameters can be measured and added to the values obtained to improve precision if required.

Preferred embodiments of the invention will now be described with reference to the Figures in which:

Brief Description of the Drawings

Figure 1 illustrates a block diagram of a quasi-sine resonant drive;

Figure 2 illustrates a more detailed circuitry of power components of the quasi- resonant drive of Figure 1 ;

Figure 3 shows one phase of a waveform applied to a motor running at high speed with retarded turn on of a complementary switch;

Figure 4 shows one phase of a waveform applied to a motor running at high speed with minor complementary switch turn on retardation;

Figure 5 shows one phase of waveform applied to a motor running at high speed with complementary switch turn at ideal instant;

Figure 6 shows one phase of a waveform applied to a motor running at high speed with premature complementary switch turn on;

Figure 7 shows a block diagram of a quasi-sine motor drive;

Figure 8A shows a starter circuit for the self-adjusting drive circuit;

Figure 8B shows spare components and inter-wiring information for the self-adjusting drive circuit; Figure 8C shows a reset circuit for the self-adjusting drive circuit;

Figure 8D shows a threshold detector and logic circuit for the self-adjusting drive circuit;

Figure 8E shows an auxiliary gate driver output circuit (hard and soft) for the self- adjusting drive circuit;

Figure 8F shows a main gate driver output circuit (hard and soft) for the self- adjusting drive circuit;

Figure 9 is an overall view of a turn on circuit shown in Figures 8C and 8D;

Figure 10 shows a circuit diagram of a starter isolation circuit for the self-adjusting drive circuit;

Figure 1 1 shows an auxiliary gate driver output circuit in its low output state for the self-adjusting drive circuit;

Figure 12 is a circuit diagram of part of the self-adjusting drive circuit for enabling soft turn-on or hard turn-on of a driven switch;

Figure 13A shows an under-energised resonant waveform and block diagram of inputs required to enable oscillation.

Figure 13B is an overall diagrammatical representation showing a sequence of events that enables oscillation to occur;

Figures 14A to 14H show portions of a circuit diagram of a self-adjusting control circuit;

Figure 15 illustrates a sequence of events that enables oscillation to occur where output voltage is 50% or less of input voltage;

Figure 16 illustrates current excursions for operation of a control circuit that allows net current in or out of drive connections of a driven circuit;

Figure 17 is a table showing current and efficiency values for different output loads;

Figure 18 is an example of a circuit used for sensor-less current measurement; Figure 19 shows a theoretical waveform output obtained with the circuit in Figure 18;

Figure 20 shows a theoretical waveform output obtained with the circuit in Figure 18;

Figure 21 shows an actual waveform output obtained over more than one cycle, with the circuit in Figure 18;

Figure 22 shows an actual waveform output obtained within one cycle, with the circuit in Figure 18;

Figure 23 shows an actual waveform output obtained for a single cycle, with the circuit in Figure 18;

Figure 24 is a circuit diagram of a synchronous Buck converter;

Figure 25 is signal timing diagram for the synchronous Buck converter in Figure 24;

Figure 26 is a circuit diagram of a first embodiment of a switching supply including C1 and C2 and a feedback controller;

Figure 27 is a circuit diagram of second embodiment of the switching supply with capacitor (C1 ) only;

Figure 28 is a circuit diagram of another embodiment of the switching supply without a feedback processor and with capacitor (C2) only;

Figure 29 shows signal timing diagrams for the switching supply;

Figure 30 is a signal timing diagram for the start-up phase;

Figure 31 is a signal timing diagram for the start-up phase which indicates a prohibited or indeterminate condition which is over-ruled during a first start-up cycle; and

Figure 32 shows in block diagram form, an example of a resonant voltage conversion circuit.

Detailed Description of the Drawings

Figure 1 illustrates a block diagram of a quasi-sine resonant drive. Here it is shown that the output part of the circuit, consisting of the variable frequency stage, the slew rate capacitors and the motor itself forms a resonant circuit. In order for the system to operate correctly a self-adjusting turn on of the appropriate switch is required which occurs in this quasi sine form of output. Sensors may be shown connected to the motor giving an indication of speed. This can also give an indication of torque ripple if differentiated. Alternatively motor information can be calculated or derived from other measurable parameters. The variable voltage part of the circuit, shown at figure 1 , is typically also a resonant voltage conversion topology. By using these two techniques together, extremely high efficiencies can be obtained.

Figure 2 illustrates a more detailed circuit showing power components of a quasi- resonant drive circuit. Figure 2 shows a three phase half bridge frequency determining circuit with slew rate capacitors C6, C7 and C8 arranged in parallel with their outputs connected to the motor. The voltage amplitude of the generated waveforms at the output is determined by the variable voltage part of the circuit.

In operation, at the appropriate time determined by control circuitry (shown in Figure 1 ), one of the output drive transistors, Q3, (shown in Figure 2), is turned off quickly. The current that was flowing prior to switch off of Q3 transfers to charging or discharging slew rate capacitors C6 and C8 until the voltage across switching device Q4 becomes reverse biased, at which instant diode D4 switches to conduct. Diode Q4 may be either intrinsic or external to the now reverse biased switching device.

Control circuitry (shown in Figure 1 ), now turns on switch Q4, (shown in Figure 2) and maintains it on until it is switched off quickly. This repeats the resonant switching process. This same resonant process occurs on both of the other phases of the output; or as many phases that are appropriate for the motor/generator that is being controlled (Figure 2).

The operation of output circuit, the variable frequency circuit part of Figure 2, is essentially determined by a controller (figure 1 ) which acts to force outputs to go off at a predetermined instant. Referring to Figure 2 switches Q3 to Q8 are switched on again by detecting the instant when the voltage across a switch is at zero potential, thereby ensuring no "shoot through" currents can occur. Therefore switch on occurs with no voltage potential across a switch. This ensures that there are no transient (voltage x current x dt) losses. This type of operation, where the devices are turned off by the waveform frequency control mechanism (Figure 1 ) and turned back on again by the natural resonance, ensures that all component values and tolerances are automatically taken into account in order to derive optimum input parameters to drive a system (motor), for every switching transition that occurs. Further, in one embodiment, this can be achieved without the need for a microprocessor type hardware or software burden.

The variable voltage element, shown in Figure 2 of the circuit, includes switches Q1 and Q2 and associated other components which are also operated in a resonant mode. As configured the variable Voltage circuit provides a voltage step down function from the supply across C1 .

Figure 3 shows one phase of waveform applied to a motor running at relatively high speed with turn on using an opposite (complementary) switch for example Q4 in figure 2 where the turn on signal to Q4 is too slow. Figures 3 to 6 show the importance and effect of correct timing of the turn on point of the opposite switch in relation to the turn off of the first switch. The Figures 3 to 6 also show the slew rate clearly and, because the motor speed is fast, the opposite transition occurs and the cycle repeats itself. This sequence of events, of the transition from one voltage state to the other, is identical at different voltages, currents and frequencies. The sequence is also the same sequence that occurs in the variable voltage part of the circuit shown in figure 2 as it operates to maintain a given output voltage. In Figure 3 in particular, the timing of switching of the opposite switch Q4 in Figure 2 is shown as having been delayed from switch on at the right time.

Figures 3 to 6 show the effect of the resonance of the shunt capacitors C6, C7, C8 in figure 2 during operation. Considering one of the 3 phase outputs to the motor in Figure 2, when Q3 is turned off, the motor phase current is being maintained by a combination of the displacement current in C6 and C8 and the forward conduction of the parallel diode D4 across the opposite switch Q4. When this current is reversed and flows into the motor and if switch Q4 is not closed then resonance occurs in the opposite direction of the voltage applied to the motor. When the switch Q4 conducts either before D4 is in conduction or after the motor phase current has changed direction then there is a very rapid change of voltage across switch Q4 that occurs at the same time with a large current pulse (not shown) in switch Q4. This current pulse can reach destructive levels if switch turn on time is very short and the switch impedance is low enough.

Even if when this potentially destructive switching is not a problem, the switching devices experience significant repetitive transient switching losses that are proportional to: volts x current x switching time. There are therefore significant issues with sharp edge of such voltage transitions with cable resonances, EMC radiation and dV/dt stress applied to motor windings.

Figure 4 shows one phase of waveform applied to a motor running at high speed with turn on of opposite switch, for example Q4 in Figure 2, very slightly too slow. As the opposite device Q4 is turned on closer to an optimum instant, undesirable voltage transitions become smaller (lower amplitude) with consequent smaller unwanted harmonics.

Figure 5 shows one phase of waveform applied to a motor running at high speed with turn on of opposite switch Q4 at an ideal instant. The waveform is the ideal voltage waveform. It is important that the turning on of the opposite device Q4 occurs at some point when the motor current is still flowing through the forward conduction of the diode connected across the opposite device. Ideally if the switching device is also capable of conducting current in the reverse direction (for example a field effect device) then it is advantageous to turn the switching device on as soon after the forward conduction of the diode has taken place. This is beneficial from a losses point of view if the value of (reverse current x device on resistance) is less than the voltage drop across the diode at this current level. Also switching in this manner allows for ease of optimising the On switching time of the opposite switch Q4.

Figure 6 shows one phase of waveform applied to a motor running at high speed with turn on of opposite switch Q4 very slightly too early before the resonance has forward biased D4. Here the opposite device has been switched on slightly in advance of the optimum turn on time. The resonance has not yet delivered the voltage to opposite device Q4 to drive it negative. When this occurs it gives rise to a high transient current in the opposite device Q4; causes excessive device switching losses: and is the source of problems associated with a fast edge, rather than the relatively smooth and slow edges associated with the resonant circuit operation. Note that the correct timing of the on switching event is not related directly to the frequency of the drive. The correct time to turn the switch on is at instant shown in Figure 5.

Figure 7 shows a block diagram of a quasi-sine motor drive. This shows the position of a self-adjusting switching device driver described as a self-triggering turn On' circuit. In Figure 7 there are 3 motor phases so there are 6 switching devices shown as 1 to 6. Each of these switches is controlled by 6 self-triggering turn on circuits which are more fully described with reference to the circuit in Figures 8A to 8F . It is possible to drive switching devices 1 to 6 directly on and off by calculating switching criteria. However the self-triggering drive circuit described inherently compensates for turn on timing for each switching event and thereby automatically takes into account variables that would make a calculation based decision too complicated and therefore too time consuming to perform. These variables include: coil, motor, shunt/resonance capacitor, speed, load, voltage, current, temperature or any combination thereof.

Where the individual switching device is shown, there may in fact be several devices in parallel. Under these conditions it may be possible to have (within the switching device drive circuit) one part that detects the instant to switch on the devices and one or more driver circuits, for example one driver circuit for each switch in a parallel arrangement. Furthermore some of the drive circuits need to be floating while others have a common connection and so in some configurations it may be possible to employ circuit redundancy and so save components, cost and weight. Also an overall control microprocessor identified as 'μ' may optionally be referenced to the low voltage common terminal connecting switches 2, 4 and 6 of the power circuitry thus eliminating a significant amount of unnecessary signal isolating components.

Figures 8A to 8F depict automatic turn on circuitry to achieve optimum turn on timing of its associated power switching device. The circuit is used in an example of an automatic self-adjusting motor drive system.

Figures 8A to 8F show views of a circuit diagram of a complete self-adjusting drive circuit. This design incorporates fundamental aspects of the turn on detection circuitry. It has one input (reset) that is basically a 'must turn off and stay off command input. The circuit in Figures 8A to 8F has one input (drain/collector) that measures the voltage across the switching device to be controlled. It has an optional input (starter) that allows the switching device associated with it to be turned on slowly irrespective of any reset and drain/collector status. The circuit in Figures 8A to 8F have power supply pins which are nominally at 12 volts. It has one or more outputs to enable the switching devices to be switched on or off.

Figure 9 is an example of a reset circuit of the type that may be used in the circuits detailed in Figures 8A to 8F. An important feature is the bi-stable element U1 a. A reset on pin 4 under normal running conditions overrides any status of the switching device itself. The wiring and polarity of the connection to the reset opto-coupler U6 is failsafe. The voltage detecting circuit for the drain/collector ideally has variable impedance. The advantage of this is for the detection circuit to present a very low impedance to the switching device drain/collector while diode D8 is reverse biased. This eliminates the possibility of high frequency noise leaking through the reverse biased diode and causing a false zero volt detection to occur. This low impedance can only be overcome when the diode is properly forward biased which can only occur when the voltage across the switching device is about zero volts. The circuit itself operates at low voltage except for the cathode of diode D8.

Figure 10, Figure 11 and Figure 12 show detailed views of the starter and driver circuit used in Figures 8A to 8F. The way these work is that in mode A, gate of associated switching transistor is turned on slowly so that a current spike (from charging or discharging shunt (C6, C7, C8 in Figure 2 for example) or other resonant capacitors) does not cause a significant current spike in the associated switching device of such an amplitude that it stresses or in a worst case destroys the associated switching device. Actual one shot energy loss here is not detrimental to the associated switching device. With motors, all three phases can be started separately at reduced voltage (and at the same output voltage). Different conditions apply for quasi sine and pure sine drives.

The starter circuit in Figure 10 is operable even if the voltage conditions across the device are considered inappropriate for normal operation of the turn on circuit as shown in Figure 9. Care must be taken to ensure that inappropriate operation of this circuit cannot occur. Figures 11 and Figure 12 are detailed views of a power transistor drive circuit used in Figures 8A to 8F. In this particular implementation, the circuitry in Figures 8A to 8F is capable of operating two independent power switching transistors. The circuits in Figures 11 and Figure 12 have the capability of either mode a: soft high, or mode b: hard high, operation. In both cases Figures 11 and Figure 12 have a hard/low capability.

In the circuit of Figure 1 1 , the switch driver U5 has two outputs. One output is connected to pin 6 and pulls current out of the associated switching device to turn it off, thereby effectively driving the gate/base low. This output has a very low impedance and thus switches the associated switch very quickly, typically within around a few 10s of nanoseconds. High output from pin 7 is effectively off so no positive current can flow through R5 or R6.

For stability and control reasons it may be beneficial for the soft turn on, mode a, to only use one transistor in an output switch consisting of multiple parallel connected power devices. In this implementation both the circuits shown in Figure 1 1 and Figure 12 are capable of doing this. A simple logical modification allows only the circuit in Figure 12 to have a soft turn on mode a.

Figure 12 in mode a operation is a detailed view of a power transistor drive circuit used in Figures 8A to 8F with particular attention being paid to its soft turn on capability when there is a high voltage present across the device being switched on. This part of the circuit is used for the initial starting phase of resonant operation. A problem it overcomes is how to start a resonance system that has no inherent mechanism to do this, as turn on pulses are generated by the action of resonance itself once resonance has been established. Therefore simply enabling the transistors does not switch them on as none of the switches Q3 to Q8 (Figure 2) are unlikely to be sitting in a suitable quiescent state with no voltage across them.

Under these conditions, the voltage of the switching transistor is unknown and so the zero voltage detecting circuit is inhibited. When the soft start input is enabled, mode a operation, there are two switches in a totem pole like output configuration. The other switching device in the totem pole is turned off so there is no possibility of a shoot through condition occurring. D4 inhibits a so-called 'strong pull up'. This leaves R20 to limit the input current into the combined capacitance of both the input capacitance and the Miller or reverse transfer capacitance of the switching device as it turns on.

This slow turn on minimises the peak current that results from discharging the shunt capacitance across the switching device. In the sequence of operation of the startup, the system firstly applies off pulses to both top and bottom transistors of the totem pole like output configuration, selects a transistor to turn on and applies a switch on current to the soft start input which bypasses latch U1 a in Figure 8D and applies a soft start pulse to the selected transistor. This soft on pulse bypasses the latch U1 a in Figure 8D and 'hard on' driver so as to apply a soft pulse in order to avoid capacitive current from the shunt capacitor from destroying the selected transistor.

To start the three phase quasi-sine system it may be necessary to initialise the system and set it up for commutation by connecting one phase of the motor to the positive rail and the other two phases to the negative rail in order to inject current into the motor to enable resonant commutation to commence once the appropriate Off pulses are initiated. For the quasi sine implementation, for minimum components it is convenient to turn on one of the pull up output transistors as they tend to be at a high voltage potential and so require isolated drive capability. The other two legs of the 3 phase half bridge are switched to the common negative rail and therefore do not require extra isolation components.

Figure 12 in mode b operation, is a detailed view of a power transistor drive circuit used in Figures 8A to 8F with particular attention being paid to its hard (fast) turn on capability when there is a negligible voltage present across the device being switched on. Here pull up transistor Q3 is enabled, D4 is reverse biased, and R1 1 is switched high so a strong turn on current to the switching device is provided via R17. This is the normal turn on mechanism that is enabled by the voltage across an appropriate switching device reaching zero volts. This soft or hard turn on option is required for both the circuitry involved in driving and controlling the variable voltage stage Q1 and Q2 in Figure 2 as well as the circuitry involved in driving and controlling the variable frequency stage Q3 to Q8 also depicted in Figure 2.

Figures 13A and 13B depict diagrammatically a sequence of events that enables oscillation to occur. When the circuit is at rest, all switching devices have their resets enabled. To start the resonant circuit it is initially required to generate pulses of a suitable duration and apply them to the appropriate switching devices while other switching devices not required for the initialising process are still held in their reset conditions. This tends to charge up inductors in the circuit with sufficient current to enable a positive voltage rail to negative rail excursion to be able to occur with the associated resonant capacitors shunted across the switching devices. At this moment the opposite switches have to be enabled so that when the original switching devices are turned off, voltage detection circuitry operates correctly by detecting a very near zero state and turn the opposite switching device on. From this point circuits (shown for example in Figures 2, 8A to 8F and 14A and 14B continue to resonate. The opportunity to allow for the turn on time of the drive circuit can be allowed for by triggering its inception at a voltage point in advance so allowing for delays.

The strategy adopted is always to be turning off the appropriate devices when a target current is achieved. This is decided by the control system shown in Figures 14A and 14B. The fact that devices are resonating gets it turned on again.

This method of commutation can be controlled by software. In such an embodiment there is little chance of 'shoot through' caused by uncertainty of device switching speeds and tolerances. Therefore this method of commutation eliminates all overlap and dead band timing issues that conventional switching systems suffer from.

Because of the way the resonant circuit (in Figure 13B) operates, any stray or inherent capacitance of the switching devices, motor, cable or inductors or any other components connected to node, in this case the junction of the common connection between Qt and Qb in Figure 13B that is being switched, is in parallel with an additional capacitance component required to make the circuit function correctly. A normal switching topology finds these stray and inherent capacitances to be significantly detrimental to idealised operation and so introduces a significant power loss as well as circulating currents and EMC issues.

The turn off pulse to switching device driver circuit Figure 8C reset on PL5 has to be of a duration that is sufficient for an associated switching transistor connected to PL2 in Figure 8E to be switched off (cease conducting) and so that voltage across the collector/drain of this switching transistor to have risen sufficiently so that the voltage zero detection circuit connected to Q drain/collector on Figure 8C does not allow this switching transistor to be turned on again when turn off pulse (Figure 8C) is removed. The duration of this pulse is very small compared to the pulse repetition frequency of consecutive reset pulses applied to reset PL5 in Figure 8C so this is relatively straightforward to implement. Additional blanking gating or status feedback of latch U1 a in Figure 8D could be reported back to control circuitry in Figure 1 4A and 14B and could be used here if necessary for ultra safety critical requirements such as aerospace.

Figure 13A shows an under energised resonant waveform and block diagram of inputs required to enable oscillation. It is a requirement for correct operation of the resonant circuit shown in Figure 13B that at all times there is sufficient stored energy in the Inductance shown in Figure 13B to ensure correct rail to rail commutation. Occasional use of the soft input PL1 in Figure 8A could be used to provide the soft voltage change shown as Vadd in Figure 13A.

If voltage VQ does reach the top rail voltage in addition to the forward voltage drop of the protection power diode D1 , then the circuit in Figure 13B detects the peak of the resonance of the voltage QV and when this occurs it turns switch Q1 softly on at this instant. The diagram illustrates the situation that occurs during the start-up phase when a prohibited or indeterminate condition is over-ruled for a first start-up cycle in order to commence oscillation.

It is possible that the voltage VQ peaks below the top rail voltage Vin, depending on such factors as: the value of L, the value of C2 and C4, the amount of delay imposed by criterion b), the energy present in the inductor L when Q2 is switched off, the relative values of Vout and the top rail voltage, and the current drawn by any load connected to the output. The circuit in Figure 13B detects if voltage VQ peaks below the top rail voltage plus the forward voltage drop of power protection diode D1 and turns switch Q1 on at this time. Advantageously this is when the voltage drop across switch Q1 is minimized and therefore the switching power loss (and RFI) are also minimized at this time.

Figure 13A shows an under-energized resonant waveform and block diagram of inputs required to enable oscillation.

Figure 13B shows the power stage that is controlled by the control circuit Figure 1 4A to 14H. Figure 14 shows a circuit diagram of self-adjusting voltage control circuit. This is used in the variable voltage section as shown in Figure 2. In order to derive the desired voltage, variable volts output, from the circuit in Figure 2, the control circuit (shown in Figures 14A to 14H) compares an output voltage with the required target voltage shown in Figure 14A. From this it ensures that off pulses, applied to the two switching devices Q1 and Q2, (shown in Figure 2) in order to maintain the output voltage at a desired level. A reset circuit as shown in Figures 8A to 8F for a resonating circuit (of the type shown in Figure 2) includes a control circuit operative to continually reset a latch in order to force the latch to an off state, whereby the condition of an output transistor, for example Q1 in Figure 2, which is controlled by latch U1 a in Figure 8D is switched off. Shortly after switch off of transistor Q1 , the control circuit in Figures 8A to 8F isolates the reset signal so that transistor Q1 is not triggered on again until the voltage across device Q1 reaches zero.

The circuit shown in Figure 14A and b is analogue but it could be converted partly or completely to a digital domain if required. The fundamental aspects of operation would be unchanged. In Figure 2, the variable voltage supply output is capable of operation from one voltage rail to the other and has a full power bandwidth of several kHz in this configuration. The full power bandwidth can be increased to many kHz. The resonant operation used has no inherent high frequency limitation. The high frequency range is limited primarily by turn off speed of the switching devices.

The switching devices have to turn off completely, within a few percent of their rise time, which is dictated by slew rate capacitance and operating current. Switch off times slower than this tend to waste power in the switching devices as they have to handle a repetitive switching loss where there is both voltage and current present for a period of time in the switching device. The resonant operation overcomes this under normal conditions, effectively by bypassing the current that is present as the device turns off, into becoming the charging or displacement current of the resonant shunt capacitors both deliberate and parasitic.

The circuit in Figure 14A to 14H has several important features and functions. Controlling a resonant circuit so that it always resonates under all conditions of applied input power voltage, desired power output voltage and desired output current requires a radically different kind of control strategy. This is especially so if extremely high levels of conversion efficiency are to be achieved.

Loop gain stability under all conditions has been one of the most difficult issues to control. This is particularly so where a high full power bandwidth is required as near to critical damping as possible whilst still maintaining operation of a resonant circuit.

Assuming that the desired target voltage is presented to the circuit (in Figure 14A) as a 0 to 5 volt value with a midpoint of 2.5 volts. Knowing what the power input mean voltage value is, then the centre point of the voltage output (which is half the voltage input) can be set by adjusting an 8 bit attenuator pad U4 and U13. Any error between the attenuated output voltage and the target input voltage is developed as an error signal from the differential amplifier U10b as shown in Figure 14A. This error is developed across C6 after modification for loop gain and the response time by the variable gain elements controlled by U14 a, b and c. This error voltage is amplified by amplifier U7a which nominally sits at 2.5 volts if the input and attenuated output voltages are identical. Any deviation from this tends to cause the voltage at U7a to vary from 0 to 5.0 volts.

It is important to consider the idling state of variable voltage resonant circuit shown in figure 2 while it is running at a particular voltage output but where no net current is being drawn from its output terminal. The control circuit in Figure 14A and b gives an output voltage that is exactly equivalent to the current flowing in the coils of the output inductor L2a,b in Figure 2. The circuit shown in Figure 14G is discussed in greater detail below and in combination with Figures 18,19 and 20. Under these conditions the timing of the off pulses to the switching devices Q1 and Q2 is arranged so that the current in the inductor builds up to a certain positive level at which point outputs from circuit U3a and b in Figure 14H toggle and coil current drops to zero and then increases to an equal and opposite value to the current on the previous half cycle.

At the corresponding negative point the outputs of U3 a and b again toggle and the coil current in L2a,b in Figure 2 becomes less negative, crosses zero and increases to its original positive value again. This cycle then repeats. Any minor errors in currents and timing result in the variable volts output voltage drifting up or down and the voltage discrepancy causes the off times of each switching device Q1 and Q2 to be altered slightly. This tends to force the variable volts output voltage to its correct value. This continual oscillation and shuttling of current back and forth has sometimes been considered wasteful but the inherent losses are so small in this kind of resonant topology. Even with relatively small output powers, in relation to full power capability, the overall efficiency is extremely high. The offset circuit comprises two comparators U3a and U3b in Figure 14H which compare two adjustable voltages so that when power is required, a feedback controller U7a offsets the voltages by a predetermined amount in order to derive more/less power which is proportional to the offset.

Because of the unusual topology and the control strategy adopted the variable volts output circuit shown in Figure 2 operates in all four quadrants. In the circuit in Figures 14A and 14B, a careful analysis of the voltage outputs of U5a and b, U7a and b, and the networks on pins 2, 3, 5 and 6 on comparators U3a and U3b identify that the outputs 1 and 7 of U3 provide the correct off pulses when required.

Figure 15 depicts the sequence of events that enables oscillation to occur where output voltage is 50% or less of input voltage. A particular problem that has to be overcome in this resonant topology is that when current flows from the output, say the variable volts output in Figure 2 and the output voltage is at about 50% or less of Vmax, where Vmax is the voltage at A, there is required an injection of negative current (Irev) introduced into the resonant inductor L2a,b for resonant commutation to occur. Without this negative current, there is not enough energy to resonate shunt capacitors C4 and C5 so that the opposite switching device is reverse biased sufficiently to trigger the on pulse and ensure lossless commutation to continue.

This negative current lev needs to be increased as the output voltage decreases. This negative current is derived from the specific operation of amplifier U5a and depends on the output polarity of U7b and the network values at input of comparator U3. The configuration in Figure 14A and 14B also allows for normal operation where output voltage is 50% or higher and the current flows into the output terminal.

Figure 16 shows the coil L2a,b current excursions for operation of the control circuit Figure 14A and 14B for allowing net current in or out of variable voltage output connections in Figure 2. When the variable voltage circuit in Figure 2 is in its resonant idling mode, the current flowing into and out of resonant inductor L2a,b is equal and opposite, thus giving no net current flow either into or out of the variable volts output terminal. As current is drawn from the variable volts output terminal, the output voltage tends to fall and feedback circuit U10b, U7a and associated components acts to offset the switching points at turn off for comparators U3a and U3b. In turn these results in a higher value of positive current, and a lower value of negative current, flowing thus giving the desired net current outflow. Initially the control circuit in Figure 14A and 14B, attempts to maintain the same overall switching frequency, typically up to the point that the coil current doubles in the positive direction and drops to zero on the negative phase of the cycle.

If more current is required then the positive current increases to its maximum of, say 4 times peak idle current, while still maintaining its minimum current at zero. Consequently when more power is required it is necessary to reduce the input frequency of this system. This is helpful as the coil losses increase due to the higher currents but are reduced due to the lower frequency of operation.

As the circuit operates in all four quadrants, for full current in the negative direction the triangular wave is displaced below the zero current line.

Figure 17 shows the current and efficiency calculations for the level of loading on an output. Figure 17 shows how this unusual effect of efficiency versus loading characteristics that this resonant topology achieves. This efficiency is aided by altering the internal current ramp offset and the frequency change under load to achieve the efficiency range.

Figure 18 is an example of a circuit used for sensor-less current measurement. It overcomes the use of conventional current measurement techniques which introduce series resistance and amplifiers. Alternatively the circuit in Figure 18 may be used to measure the passage of current by the use of a Hall effect principles. It can be difficult to obtain the current to be measured itself because of voltage offsets or high dV/dt issues superimposed on the current. As a consequence there can be significant power losses as well a time delays which can impinge on loop stability and limit the speed of operation of the circuitry.

The use of physical current measuring techniques can also cause problems in layout of the circuit and some of the sensors themselves are sensitive to stray electrical and magnetic fields. From this evolved the necessity to develop an improved current measuring technique.

The block diagram in Figure 18 illustrates where a voltage at the coil terminal A is significantly higher than the voltage at B, then the current into the capacitor C1 at B is closely approximated to (VoltsA/R1 ). From this it can be calculated that the change in coil current dl is equal to ((C1 x R1 )/L) x dVd where Vc1 is the voltage change across C1 .

So ignoring any offset issues, the voltage waveform across C1 is identical to the current waveform in the inductor L. However it is necessary to include a voltage clamp on this waveform at every ½ cycle, as an integrator has no absolute DC value.

The next stage in the sensor-less current measuring method is to determine the absolute values of the current and these can be determined at each time the coil current in L2a,b in Figure 2 resonates shunt capacitors C4 and C5 across switching devices Q1 and Q2. At this point the inductor current can be determined from the rate of change of voltage at the instant of commutation.

(I inductor/C shunt) = dV/dt at point A.

Cshunt = Cstray + Cdevices + Cdeliberate

Passing the switching edge at point A in Figure 18 through differentiator C2, R2 and associated amplifier, the voltage across C2 and R2 gives a voltage at C which is proportional to the absolute current in inductor L2a,b at the point of switching off. This voltage is then used to restore the direct current (DC) current waveform at B by operating switch D at the zero cross of voltage A.

Figure 19 shows a theoretical waveform output obtained with the circuit in Figure 18. Here inductor L2a,b has two different current values. The first is at negative going transition and is at a relatively low current. Therefore the slew rate of shunt capacitors C4 and C5 is relatively long. This lengthy slew rate translates to a relatively small voltage at C. The second transition occurs at a high inductor current and so the slew rate is relatively fast. This faster slew rate translates into a much narrower, but higher amplitude, pulse at C. Figure 20 shows a theoretical waveform output obtained with the circuit in Figure 18. Here the relationship between the voltage at B and the inductor L2a,b current related voltage C is DC restored at the clamping point D.

Figure 21 shows an actual waveform output obtained with the circuit in Figure 18. It shows the voltage at C derived from the inductor current at the switching point superimposed on the voltage waveform at B.

Figure 22 shows an actual waveform output obtained with the circuit in Figure 18. Figure 22 shows an expanded trace of the voltage waveform at B superimposed with inductor voltage at A as it crosses the zero volts axis. It can be seen that a DC restore clamping point, shown as two vertical lines in Figure 22, derived from this zero point is the optimum point to perform DC restoring as it occurs at the peak of voltage waveform at B.

Figure 23 shows an actual waveform output obtained using the circuit in Figure 18. Referring to Figure 21 this illustrates the desirability of performing DC restore at the inductor zero voltage point. Here a very non symmetrical inductor voltage A is used and the zero crossing point very closely identifies the peak of the current waveform at B.

Figure 24 shows an example of a synchronous Buck converter which comprises a power switch illustrated by transistor Q1 and an auxiliary switch illustrated by transistor Q2. A DC supply provides a constant voltage Vin. Output stage consists of an inductor shown as coil L and an output capacitor C4 in series. A load impedance, Zioad, is connected in parallel with the output capacitor C4. The junction between Vin positive and the power switch Q1 is referred to herein as the top rail. The voltage of the top rail is Vin. Junction at the output to the auxiliary switch Q2 and the negative of Vin is referred to herein as the bottom rail. The voltage of the bottom rail is ground in many, but not all, applications. For the purposes of the present embodiment the voltage of the bottom rail is zero.

Referring again to Figure 24, the mutual junction of switch Q1 , switch Q2, and coil L is designated junction Q and the voltage at this junction is VQ. The junction of coil L and output capacitor C4 and load impedance Zload is designated the output junction. The voltage at this junction is designated Vout. The current passing from junction Q through coil L to the output junction is designated IL.

Connected in parallel across switches Q1 and Q2 are protection diodes D1 and D2. Protection diode D1 is in parallel with switch Q1 and protection diode D2 is in parallel with switch Q2. Protection diode D1 is arranged to block current if the voltage at the top rail is higher than the voltage at junction Q. Current only flows through diode D1 if the output voltage VQ is greater than Vin + D1 diode forward voltage drop across Q1 .

Protection diode D2 is arranged to block current if the voltage at junction Q is higher than the voltage of the bottom rail. Current only flows through diode D2 if VQ is less than the bottom rail voltage less the D2 diode forward voltage drop voltage across Q2.

As illustrated in Figures 24, 25, 26, 27 and 28 inclusive, the current IL flowing through the inductor L is considered positive when it flows from junction Q to the output junction. That is inductor current IL is said to be 'forward' when it is flowing from junction Q to the output junction. The current IL flowing through the inductor L is considered negative when it flows from the output junction Q to junction Q. That is inductor current IL is said to be 'reversed' when it is flowing from the output junction to junction Q. If the inductor current IL is said to be increasing positively, it means that its magnitude is increasing while it is flowing forward. If the inductor current IL is said to be "increasing negatively", it means that its magnitude is increasing while it is flowing reversed.

Figure 25 shows a signal timing diagram for the synchronous Buck converter. It shows the way that voltages and currents change in this circuit over time. Using Figure 24 for reference, initially the voltage VQ and Vout are zero; the top rail voltage is Vin; the bottom rail voltage is zero; current IL is zero; and switches Q1 and Q2 are both off. In the first mode the power switch Q1 is turned on and the auxiliary switch Q2 is off. Then voltage VQ is equal to the top rail voltage Vin. If switch Q1 is a transistor, then voltage VQ is not exactly equal to Vin due to semiconductor effects. The current IL, through the inductor, rises. This rising current charges the output capacitor C4. The voltage Vout rises. Upon reaching an upper desired level for IL, power switch Q1 is turned off and auxiliary switch Q2 is turned on. In the second mode the power switch Q1 is off and auxiliary switch Q2 is switched on. Voltage VQ is equal to the bottom rail voltage which is zero. If switch Q2 is a transistor, then voltage VQ is not exactly equal to zero due to semiconductor effects. The current IL through the inductor falls because the voltage Vout is higher than VQ. Although the current IL through the inductor is falling, it is still flowing into output capacitor C4 through output junction. Therefore the voltage on the capacitor C4 continues to rise initially. However if auxiliary switch Q2 is left on long enough, the current through the inductor L eventually drops to zero. Therefore the voltage at the output junction Vout keeps rising until the current through the inductor L reaches zero, at which instant voltage Vout stops rising.

If continuous operation of the circuit in Figure 24 is required, it is important that the coil current is not allowed to fall to zero, and under these conditions auxiliary transistor Q2 is turned off and Q1 is switched on again while current is flowing through the coil L, thereby enabling the cycle to repeat. Note that this means there are problems associated with this such as reverse recovery losses in D2 and switching losses in Q1 due to the simultaneous presence of voltage and current in Q1 as Q1 is switched.

If discontinuous operation of the circuit in Figure 24 is required, the coil current is allowed to fall to zero; at which point in time the auxiliary transistor Q2 is turned off and transistor Q1 is turned on thereby enabling the process to repeat. The first mode is then repeated with the power switch Q1 on and auxiliary switch Q2 switched off.

By continuous repeated operation of the first and second mode of operation the output voltage Vout rises to the desired voltage and is maintained around the desired voltage by the controller in Figure 24 adjusting the drive timing to transistors Q1 and Q2 on and off thereby effectively adjusting the inductor current value IL.

An example of a prior art drive circuit is described by Panda, Pattnaik, and Mohapatra in the International Journal of Power Management Electronics, Volume 2008, Article ID 862510, in the article entitled "A Novel Soft-Switching Synchronous Buck Converter for Portable Applications". Such prior art switching converters suffered from: auxiliary switches being turned off whilst they conducted current. This resulted in switching losses and EMI. The power switch that is described with reference to Figure 24 and is one of the preferred embodiments described herein. It operates with higher peak current stress and more circulating current, as well as active and passive circuits that are more complex than existing power circuits.

Although developments in switch mode supplies have resulted in designs of considerable ingenuity, they normally suffered from increased complexity, cost or exotic components.

Figure 26 shows an embodiment of the switching supply in addition to the elements and connections of the synchronous Buck controller. The circuit also comprises a first switch capacitor C1 connected in parallel across the terminals of the first switch Q1 ; a second switch capacitor C2 connected in parallel across the terminals of the second switch Q2; and a rail capacitor C3 connected between the top rail and the bottom rail.

The switching supply also comprises a feedback controller. The feedback controller receives inputs. The switching supply sends a control output, that is based on the values and timing of the inputs, which turns the switch Q1 on or off or and sends a control output signal which turns the switch Q2 on or off.

Figure 26 is a circuit diagram of a first embodiment of a switching supply including C1 and C2 and a feedback controller. The circuit in Figure 26 has the advantage of only requiring a voltage rating for components being used at the highest voltage present when the circuit is operating; not twice that voltage which was previously the case.

Figure 27 is a circuit diagram of second embodiment of the switching supply with capacitor (C1 ) only.

Figure 28 is a circuit diagram of another embodiment of the switching supply without a feedback processor and with capacitor (C2) only.

For the sake of simplicity reference will now be made to the circuit in Figure 28 in which the value of C2 is the combined value of C1 and C2 shown in Figure 26.

Referring again to Figure 25, after the power switch Q1 is turned on, capacitor C2 is charged to the top rail voltage Vin almost immediately and voltage VQ is equal to the top rail voltage Vin. If switch Q1 is a transistor, then voltage VQ may be just slightly less than Vin due to semiconductor effects.

The circuit in Figure 24 is now described in its second mode of operation.

Current IL through the inductor rises. This rising current charges the output capacitor C4. The voltage Vout rises. The near step increase in voltage at VQ at the start of the first mode causes the output voltage Vout to rise.

The shape of the wave forms over time, including voltage VQ, voltage Vout, and current IL are shown in the signal timing diagram of Figure 25. Upon the first to occur of either of the following events power switch Q1 is turned off. The first event is the current through the inductor rises to a predetermined maximum, ILmax. The second event is an upper desired level for Vout is reached.

The maximum current in inductor L (ILmax) is limited by magnetic saturation, overheating of the inductor L, exceeding the peak current rating of Q1 or any other limiting parameter chosen. The second mode ends and the third mode begins when power switch Q1 is turned off. Preferably Q1 is turned off quickly. When this occurs Q1 is turned off and the resistance of switch Q1 increases quickly. At this instant inductor current IL, that was flowing through Q1 , is transferred to flow through capacitor C2.

In the third mode the power switch Q1 is off and the auxiliary switch Q2 is also off.

At the beginning of the third mode the inductor current IL continues to flow which draws down the voltage VQ by draining charge off capacitor C2. Voltage VQ decreases according the relation between voltage and a resonating series circuit of the inductor L and capacitors C2 and C4. An advantage of drawing charge from capacitor C2 is that there is no resistive power loss. If this function were to be provided by the turn off of Q1 , in the usual manner, the simultaneous application of voltage across and current through the switching device would result in a substantial power loss only limited by the speed of the switching event itself.

When the voltage VQ decreases to a relatively small level, below the bottom rail voltage, the protection diode D2 in switch Q2 is suddenly forward biased. This small relatively level is about 0.7 V and depends on the particular specification of diode D2. Therefore the voltage at VQ drops to a minimum voltage of about -0.7 V and can fall no further. Detection of this predetermined minimum level of voltage VQ is a criterion for turning Q2 on.

Referring again to Figure 28 upon detection of the predetermined minimum level of voltage VQ, auxiliary switch Q2 is turned on quickly. This is now the beginning of the fourth mode. Advantageously by turning auxiliary switch Q2 on at this time the voltage drop across switch Q2 is minimal because the current that was flowing through D2 can now be routed through Q2 if its impedance to this current is less than that presented by diode D2.

The action of the circuitry at the end of mode 2 and during mode 3 has therefore effected a lossless transition of VQ from the top rail voltage to the bottom rail voltage with a waveform shape dictated by the resonant values of C2, L2 and C4, and by the rail voltage and coil current at the moment of switching. Switching losses are substantially reduced and are limited to losses in the equivalent series resistances (ESR) of the components involved. Radio frequency interference is considerably reduced due to the lower dV/dt of the switching edge. All stray and parasitic capacitances in the circuit are additive to the effect of the shunt capacitance C2. This means that any stray capacitance that is effectively connected to the node at Vq such as the capacitance of Q1 in its off state for example.

The third mode ends and the fourth mode begins when auxiliary switch Q2 is turned on. At this time Q1 is off and Q2 is on.

Because the voltage VQ is about zero volts, which is less than the output voltage, Vout, the current IL through the inductor L continues to decrease. Depending on the output voltage Vout, which is the voltage on capacitor Cout, switch Q2 stays on until either of the two criteria a) or b) below occurs. a) The point in time where the inductor current IL reaches zero and when the output voltage Vout is in the range of being greater than or equal to half the top rail voltage Vin.

In practice, to allow for resonance losses, Vout needs to be slightly greater than half the top rail voltage Vin to allow a successful rail to rail resonance to occur. b) When the output voltage Vout is in the range of less than half the top rail voltage Vin, to just slightly greater than half the top rail voltage Vin, the switching behaviour of Q2 is modified. In order to route enough energy into C2 so as to commutate VQ from the bottom rail to the top rail, it is necessary to inject energy into the inductor L to achieve this.

By allowing switch Q2 to stay on past the point in time where IL drops to zero, the inductor current IL reverses and increases to a predetermined negative value. The stored energy in the inductor begins to increase again. This is the extra energy required to commutate C2 from the bottom rail to the top rail.

At the beginning of the next mode, which is the fifth mode, switch Q2 is turned off quickly. The advantage of applying criterion a or b to the turn off time of Q2 is that some of the additional energy stored in the inductor L is available to be transferred to capacitor C2 when switch Q2 is turned off. In many cases this additional energy is sufficient to eventually raise the voltage VQ to the value of the top rail voltage a certain amount of time after switch Q2 is turned off.

By this additional delay in turning off switch Q2, a stronger reversal of current is achieved through the inductor than if switch Q2 is turned off immediately upon the current in the inductor reaching zero. This stronger reversal of current through the inductor L causes additional energy to be stored in the inductor.

Advantageously some of the current that flows through the inductor when the value of the current is negative may be drawn from not just capacitor C4 but also a load connected to the output.

The fourth mode ends and the fifth mode begins when switch Q2 is turned off. During mode five switch Q1 is off and switch Q2 is off.

Referring to Figure 29 waveform is that of a damped sinusoid according to an equation corresponding to the series combination of the inductor L and the capacitor C4 and capacitor C2. Preferably the intrinsic resistance of these components is low enough for a waveform to be that of an under damped sinusoid. Due the nature of the series LC circuit resonance, the current flowing through the inductor L continues to increase negatively, at the beginning of mode 5 because the voltage VQ is about zero volts, which is less than the output voltage Vout. This adds to the energy already stored in inductor L at the beginning of mode 5 by the negative pre-charge current already flowing.

Since the current IL flowing through the inductor L is zero or negative at the start of mode four depending on whether criteria a) or b) is used to switch off Q2 at the end of mode 4, the current IL flowing through the inductor is negative immediately after mode 5 starts. This negative "reversed" current IL charges capacitor C2 and raises the voltage VQ.

If criterion a) in mode 4 triggers switch Q2 off, the voltage VQ eventually rises to the top rail voltage Vin plus an additional small voltage that is enough to forward bias protection power diode D1 . This additional small voltage is about 0.7 V above the top rail voltage depending on the particular diode D1 . Therefore the voltage VQ is limited to rising to the top rail voltage plus this additional small voltage.

This aspect of the invention therefore detects when protection power diode D1 becomes forward biased. By turning Q1 on fast at this time there is a very low switching loss since voltage drop across power switch Q1 is less than the power diode D1 voltage drop. This is the beginning of mode 2 again.

If criterion b) in mode 4 triggers switch Q2 off, the voltage VQ may or may not eventually rise to the top rail voltage Vin in addition to the additional small voltage which is sufficient to forward bias protection power diode D1 .

If voltage VQ does reach the top rail voltage in addition to the forward voltage drop of the protection power diode D1 , then the circuit in Figure 13A detects the peak of the resonance of the voltage QV and when this occurs it turns switch Q1 softly on at this instant.

It is possible that the voltage VQ peaks below the top rail voltage Vin, depending on such factors as: the value of L, the value of C2 and C4, the amount of delay imposed by criterion b), the energy present in the inductor L when Q2 is switched off, the relative values of Vout and the top rail voltage, and the current drawn by any load connected to the output. The circuit in Figure 13A detects if voltage VQ peaks below the top rail voltage plus the forward voltage drop of power protection diode D1 and turns switch Q1 on at this time. Advantageously this is when the voltage drop across switch Q1 is minimized and therefore the switching power loss (and RFI) are also minimized at this time.

Preferably to further minimize any switching loss and RFI, if the voltage VQ peaks below the top rail voltage in addition to the forward voltage drop of diode D1 , switch Q1 is turned on "softly". In this event, the resistance across switch Q1 is reduced gradually. When the voltage VQ rises to the top rail voltage, switch Q1 is then fully turned on fast.

If there is voltage undershoot of the rail target voltage, the circuit (shown in Figure 13A) can vary the pre-charge current in the inductor L by increasing the current slightly so as to ensure sufficient energy is available from the inductor to achieve correct commutation for the next cycle. This active monitoring of the resonant voltage at mode 5 allows for the control circuitry in Figure 13A to adjust the reverse or pre-charge current in the inductor L to be just enough or in excess of what is required to ensure rail to rail commutation.

At the end of the fifth mode switch Q1 is on and Q2 is off. Then the cycling process is repeated beginning with the second mode. This is shown in Figure 29.

Figure 29 is a signal timing diagram for the switching supply when the system is running.

Figure 30 is a signal timing diagram for the switching supply when the system is initiating its startup phase.

Figure 31 is a signal timing diagram for the start-up phase which indicates a prohibited or indeterminate condition which is over-ruled during a first start-up cycle.

Figure 32 shows an example of a high efficiency resonant converter device configured for voltage conversion.

The diagrams in Figure 32 show a high efficiency resonant converter circuit and its main power conversion components. In addition to components shown it is understood that an electronic drive circuit, as well as control and auxiliary power components are required to enable the circuit to operate. Due to the symmetrical nature of the circuit (Figure 32) it can be operated in all four quadrants if required. It is appreciated that the circuit can operate in four main modes.

Step down

Here the DC voltage is applied between D and C where D is the more positive terminal. The operation of the switching devices, depicted as NPN transistors, in a resonant mode allows a voltage between zero and the voltage applied at D to be available at terminal A.

Step up

Here the DC voltage is applied between A and C, where A is the more positive terminal. The operation of the switching devices, depicted as NPN transistors, in a resonant mode allow a voltage between the voltage applied at A and a voltage higher than A depending on the operating regime of the resonant circuit to be available at terminal D.

DC to AC conversion

Here the DC voltage is applied between D and C where D is the more positive terminal. If the load connected to A has its other connection connected to the midpoint of the voltage between C and D, then the operation of the switching devices, depicted as NPN transistors, in a resonant mode allows the voltage at A to be taken above or below the midpoint voltage and this impresses an AC waveform on this load with a maximum amplitude swing between zero and the voltage applied at D.

AC to DC conversion

Here the AC voltage is applied between A and returned to a point between C and a value that is equal to the peak to peak value of the AC signal present on A, where A is always the more positive terminal relative to C. The load is connected between C and D. The operation of the switching devices, depicted as NPN transistors, in a resonant mode allows the voltage at A to be taken above or below the midpoint voltage and this is converted to a DC voltage between C and D. The circuit as shown in Figure 32 for example conducts current in one direction even if the switching devices, shown as NPN transistors in Figure 32, are off. This is because of the parallel diodes placed across the switching devices in the circuit, which behave either as part of the substrate construction (in the case of a MOSFET) or are added in parallel with the switches, shown as NPN transistors, (in the case of IGBTs).

Aspects of the invention have been described by way of a number of exemplary embodiments, each exhibiting different advantageous features or benefits; and it is understood that features, components or circuits from two or more of the aforementioned embodiments may be combined together to overcome specific problems or to provide a bespoke solution to a particular problem.