BACKGROUND

Field

[0001] Embodiments relate a mechanism for terminating relay operations in a distributed switch with cascaded configuration.

Background

[0002] Various components in computer systems, such as storage components, may be connected together using a Fibre Channel protocol, a gigabit speed data transfer technology used in a variety of settings including storage systems. Fibre Channel over Ethernet (FCoE) is a technology used for transporting Fiber Channel (FC) frames over Ethernet. FCoE standards for industry have been developed and distributed by the Technical Committee for Fiber Channel of the International Committee for Information Technology Standards (INCITS).

[0003] A proposed INCITS standard "FIBRE CHANNEL SWITCH FABRIC - 6" (FC- SW-6) describes the requirements for an interconnecting Fabric comprising multiple Fabric Switch elements. Further details of FC-SW-6 may be found in the Internet based publication "http://www.tl l .org/ftp/tl l/pub/fc/sw-6/13-047v0.pdf ^* entitled "FIBRE CHANNEL

SWITCH FABRIC - 6," published February 1, 2013, by the American National Standards Institute, 11 West 42nd Street, New York, NY 10036. The version of FC-SW6 published on February 1, 2013 is referred to as the "current FC-SW-6 proposed standard dated February 1, 2013" for the purposes of this disclosure.

[0004] An FC Data-Plane Forwarder (FCDF) is a simplified FC switching entity that forwards FC frames among certain ports through a FCDF Switching Element. A distributed switch may comprise a set of FCDFs associated with at least one controlling switch, where the controlling switch controls the operations of the set of FCDFs. Certain distributed switches may be implemented in an FCoE or in a FC environment.

[0005] A distributed switch as defined by FC-SW-6 supports the concept of Cascaded switching elements. This requires an Exchange ID translation at the Intermediate switching element. The current standard does not provide a mechanism whereby an error detected on one of the exchanges between two of the switches is recovered in a way that ensures that all of the resources involved in the exchange relay can be reclaimed in a timely manner.

[0006] Therefore, there is a need in the art to address the aforementioned problem. SUMMARY OF THE PREFERRED EMBODIMENTS

[0007] Provided are a method, a system, and a computer program product in which a plurality of switches are maintained in a cascaded configuration. A switch relays a switch fabric internal link services (SW-ILS) to generate a pair of exchanges comprising a first exchange and a second exchange at the switch. In response to a termination of the first exchange of the pair of exchanges, the second exchange of the pair of exchanges is terminated.

[0008] Viewed from a first aspect, the present invention provides a method for terminating relay operations in a distributed switch with cascaded configuration, comprising: maintaining a plurality of switches in a cascaded configuration; relaying, by a switch, a switch fabric internal link services (SW-ILS) to generate a pair of exchanges comprising a first exchange and a second exchange at the switch; and in response to a termination of the first exchange of the pair of exchanges, terminating the second exchange of the pair of exchanges.

[0009] Viewed from a first aspect, the present invention provides a system for terminating relay operations in a distributed switch with cascaded configuration, comprising: a plurality of switches maintained in a cascaded configuration; a memory coupled to at least one of the plurality of switches; and a processor coupled to the memory, wherein the processor performs operations, the operations comprising: relaying, by a switch, a switch fabric internal link services (SW-ILS) to generate a pair of exchanges comprising a first exchange and a second exchange at the switch; and in response to a termination of the first exchange of the pair of exchanges, terminating the second exchange of the pair of exchanges.

[0010] Viewed from a further aspect, the present invention provides a computer program product for terminating relay operations in a distributed switch with cascaded configuration, the computer program product comprising a computer readable storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method for performing the steps of the invention.

[0011] Viewed from a further aspect, the present invention provides a computer program stored on a computer readable medium and loadable into the internal memory of a digital computer, comprising software code portions, when said program is run on a computer, for performing the steps of the invention.

[0012] Viewed from a further aspect, the present invention provides a computer program product, the computer program product comprising: a computer readable storage medium having computer readable program code embodied therewith, the computer readable program code configured to perform operations on a processor, the operations comprising: maintaining a plurality of switches in a cascaded configuration; relaying, by a switch, a switch fabric internal link services (SW-ILS) to generate a pair of exchanges comprising a first exchange and a second exchange at the switch; and in response to a termination of the first exchange of the pair of exchanges, terminating the second exchange of the pair of exchanges.

[0013] In additional embodiments, in response to a termination of the second exchange of the pair of exchanges, the first exchange of the pair of exchanges is terminated.

[0014] In yet additional embodiments, the first exchange or the second exchange is terminated by either receiving or sending an abort sequence (ABTS), wherein the plurality of switches includes a distributed Fibre Channel over Ethernet switch or a distributed Fibre Channel switch.

[0015] In further embodiments, terminating an exchange releases a pool of virtual resources corresponding to the exchange, in Fibre Channel over Ethernet or Fibre Channel.

[0016] In certain embodiments, the cascaded configuration comprises an originating switch, one or more intermediate switches, and a destination switch, wherein abort sequences are propagated both forward and backward in response to an error detected by at least one of the one or more intermediate switches.

[0017] In further embodiments, error detection is propagated in the cascaded configuration.

[0018] In yet further embodiments, all resources associated with an exchange relay are reclaimed in a timely manner.

Brief Description of the Drawings

[0019] The present invention will now be described, by way of example only, with reference to preferred embodiments, as illustrated in the following figures:

FIG. 1 illustrates a block diagram of a cascaded switch environment, in accordance with the prior art, and in which a preferred embodiment of the present invention may be implemented;

FIG. 2 illustrates a block diagram that shows an originating switch originating an Abort Sequence (ABTS), in accordance with certain embodiments;

FIG. 3 illustrates a block diagram that shows an intermediate switch originating an ABTS, in accordance with certain embodiments;

FIG. 4 illustrates a block diagram that shows a destination switch generating an ABTS, in accordance with certain embodiments;

FIG. 5 illustrates a flowchart, in accordance with certain embodiments; and FIG. 6 illustrates a block diagram of a switch, in accordance with the prior art, and in which a preferred embodiment of the present invention may be implemented.

DETAILED DESCRIPTION

[0020] In the following description, reference is made to the accompanying drawings which form a part hereof and which illustrate several embodiments. It is understood that other embodiments may be utilized and structural and operational changes may be made.

Problems with current standard and certain embodiments

[0021] A distributed switch as defined by Chapter 17 of the current FC-SW-6 proposed standard dated February 1, 2013 supports the concept of cascaded switching elements. The current FC-SW-6 proposed standard dated February 1, 2013 does not provide a mechanism in which an error detected on one of the exchanges between two of the switches is recovered in a way that ensures that all of the resources involved in the exchange relay can be reclaimed in a timely manner.

[0022] Certain embodiments provide a mechanism for propagating error detection in a cascaded switch environment in a Fibre Channel or in a Fibre Channel over Ethernet environment. In a cascaded switch environment there is an originating switch at one end and a destination switch at the other end. In between the originating and the destination switch there are one or more intermediate switches. As a command makes its way from the originating switch to the destination switch, each intermediate switch relays the command until the command reaches the destination switch. If at any point, an error is detected on a command, it may be desirable to free up the resources associated with the command not just on the detecting switch, but on all of the switches in the chain. Certain embodiments provide a mechanism for freeing up resources in all switches in the chain, in the event of an error.

[0023] In certain embodiments, in response to a request, an intermediate switch tracks the association between an incoming exchange and an outgoing exchange. This can be used to ensure that if one of the exchanges needs to be aborted due to a timeout or other error, the other exchange are also aborted.

[0024] Certain embodiments are applicable to both Fibre Channel and Fibre Channel over Ethernet environments. For the purposes of the disclosure a distributed switch is a Distributed Fibre Channel switch or a Distributed Fibre Channel over Ethernet switch.

Exemplary Embodiments

[0025] FIG. 1 illustrates a block diagram of a cascaded switch environment 100, in accordance with certain embodiments. FIG. 1 is the same as "Figure 49" of the current FC- SW-6 proposed standard dated February 1, 2013.

[0026] FIG. 1 shows an originating switch 102, and intermediate switch 104, and a destination switch 106 in a cascaded configuration. The originating switch 102, the intermediate switch 104, and the destination switch 106 may in certain embodiments be an FCDF, FDF or other type of switch as shown in FIG. 1, where FDF is for FCoE and is a FCoE data forwarder, and FCDF is for FC and is a FC Data-Plane Forwarder. The operations shown in FIG. 1 may be performed by various switches in the cascaded configuration of switches shown in FIG. 1, including the originating switch 102, the intermediate switch 104, and the destination switch 106. A switch is a device, including a computational or processing device, which can send, receive, and direct, data and commands.

[0027] In FIG. 1, the originating switch 102 sends an SW ILS request 108 to the intermediate switch 104. SW ILS refers to switch fabric internal link services. Associated with the SW ILS request 108 are a virtual pool of resources referred to as Exchange X 110.

[0028] The intermediate switch 104 receives the SW ILS request 108 and forwards a corresponding SW ILS request 112 to the destination switch 106. Associated with the SW ILS request 112 are a virtual pool of resources referred to as Exchange Y 114.

Therefore, Exchange X 110 is associated with SW ILS request 108 and Exchange Y 114 is associated with SW ILS request 112. [0029] Once the destination switch 106 receives the SW ILS request 112, the destination switch 106 sends an SW ACC 116 command to the intermediate switch 104, and the pool of virtual resources referred to as Exchange Y 118 are released. The SW ACC 116 command is an acknowledgement that releases the pool of virtual resources. The

intermediate switch 104 relays the SW ACC 116 command to the originating switch 102 by sending a SW ACC command 120 and the pool of resources denoted by Exchange X 122 is released.

[0030] Therefore, in FIG. 1 exchange identifiers (e.g., Exchange X, Exchange Y, etc.) are associated with SW ILS requests, and such exchange identifiers that denote resources are released when corresponding SW ACC commands are received.

[0031] The current FC-SW-6 proposed standard dated February 1, 2013 does not provide a mechanism where an error detected on one of the exchanges between two of the switches is recovered in a way that ensures that all of the resources involved in the exchange relay can be reclaimed in a timely manner.

[0032] In FIG. 1, the relay of an SW ILS results in a pair of related exchanges at the FCDF performing the relay. In certain embodiments proposed in this disclosure, when one of the pair of exchanges is terminated (e.g., by either receiving or sending ABTS, i.e., an abort sequence), the other related exchange is to be terminated via another ABTS. Abort sequences may relayed both backwards and forwards to release resources caused by an error in one of the switches in a cascaded switch environment. The error in a switch may be caused by a timeout or for some other reason.

[0033] FIG. 2 illustrates a block diagram 200 that shows an originating switch originating an ABTS, in accordance with certain embodiments. The operations shown in FIG. 2 may be performed by various switches in the cascaded configuration of switches shown in FIG. 2, including the originating switch 102, the intermediate switch 104, and the destination switch 106. [0034] The originating switch 102 sends (reference numeral 202) a SW-ILS request that has associated resources denoted by Exchange X to the intermediate switch 104. The intermediate switch 104 forwards (reference numeral 204) the SW-ILS request that has associated resources denoted by Exchange Y to the destination switch 106. Then the originating switch 102 detects (reference numeral 206) an error.

[0035] On detecting the error, the originating switch 102 sends (reference numeral 208) an ABTS with which Exchange X is associated, to the intermediate switch 104. The intermediate switch 104 then sends in any order the ABTS with associated Exchange Y to the destination switch 106, and a BA-ACC with associated Exchange X to the originating switch 102 (reference numerals 210, 212). As a result of the BA-ACC with associated Exchange X, the pool of resources corresponding to Exchange X may be reused (reference numeral 212), In certain embodiments, the intermediate switch 104 may wait for the exchange Y to be terminated (wait for BA ACC to ABTS on Exchange Y) before responding BA ACC to Exchange X).

[0036] The destination switch 106, on receiving the ABTS from the intermediate switch 104, sends a BA-ACC with associated Exchange Y to the intermediate switch 104, and as a result the pool of resources corresponding to Exchange Y may be reused.

[0037] Therefore, in FIG. 2, the originating switch 102 has detected an error. The originating switch 102 sends an ABTS for Exchange X. When the intermediate switch 104 receives the ABTS, it deallocates the resources assigned to Exchange X and responds with a BA-ACC to the originating switch 102. In order to ensure that all resources are deallocated, the intermediate switch 104 also aborts Exchange Y with an ABTS to the destination switch 106.

[0038] FIG. 3 illustrates a block diagram 300 that shows an intermediate switch 104 originating an ABTS, in accordance with certain embodiments. The operations shown in FIG. 3 may be performed by various switches in the cascaded configuration of switches shown in FIG. 3, including the originating switch 102, the intermediate switch 104, and the destination switch 106. [0039] In FIG. 3, the originating switch 102 sends a SW-ILS request with associated Exchange X to the intermediate switch 104 (reference numeral 302), and the intermediate switch 104 after forwarding (reference numeral 304) the SW-ILS request with associated Exchange Y to the destination switch 106 detects (reference numeral 306) an error.

[0040] The intermediate switch 104 has detected the error in certain embodiments shown in FIG. 2. In order to free up all resources, ABTS is sent (reference numeral 310) from the intermediate switch 104 to the destination switch 106 for Exchange Y and ABTS is sent (reference numeral 312) from the intermediate switch 106 to the originating switch 102 for Exchange X. The resources associated with Exchange X and Exchange Y are released when the BA-ACC acknowledgements are received (reference numerals 312, 314) at the intermediate switch 104 from the originating switch 102 and the destination switch 106.

[0041] FIG. 4 illustrates a block diagram 400 that shows a destination switch generating an ABTS, in accordance with certain embodiments. The operations shown in FIG. 4 may be performed by various switches in the cascaded configuration of switches shown in FIG. 4, including the originating switch 102, the intermediate switch 104, and the destination switch 106.

[0042] In FIG. 4, an SW ILS request with associated Exchange X is sent (reference numeral 402) from the originating switch 102 to the intermediate switch 104, and then the intermediate switch 104 forwards (reference numeral 404) the SW-ILS request with associated Exchange Y to the destination switch 106.

[0043] The destination switch 106 then detects (reference numeral 406) an error, and sends (reference numeral 408) an ABTS with Exchange Y to the intermediate switch 104. The intermediate switch 104 sends (reference numeral 410) a BA-ACC with Exchange Y, such that the pool of virtual resources associated with Exchange Y may be reused. The intermediate switch 104 may also send (reference numeral 412) in parallel or before or after the operations shown via reference numeral 410, an ABTS with Exchange X to the originating switch 102 which sends (reference numeral 414) a BA-ACC with Exchange X to the intermediate switch 104 to release resources associated with Exchange X. [0044] The destination switch 104 has detected the error in certain embodiments described in FIG. 4. In order to free up all resources, ABTS is sent to the intermediate switch 104 for Exchange Y and ABTS is relayed to the originating switch 102 for Exchange X.

[0045] FIG. 5 illustrates a flowchart 500, in accordance with certain embodiments. The operations shown in FIG. 5 may be performed by one or more of the plurality of switches shown in FIGs. 1-4.

[0046] Control starts at block 502, in which a plurality of switches are maintained in a cascaded configuration. A switch relays (at block 504) a switch fabric internal link services (SW-ILS) to generate a pair of exchanges comprising a first exchange and a second exchange at the switch.

[0047] From block 504 control proceeds in parallel to block 506 and 508. At block 506, in response to a termination of the first exchange of the pair of exchanges, the second exchange of the pair of exchanges is terminated. In block 508, in response to a termination of the second exchange of the pair of exchanges, the first exchange of the pair of exchanges is terminated.

[0048] Therefore, FIGs. 1-5 illustrate certain embodiments in which a cascaded configuration comprises an originating switch, one or more intermediate switches, and a destination switch, where abort sequences are propagated both forward and backward in response to an error detected by at least one switch. In a Fibre Channel over Ethernet configuration or in a Fibre Channel configuration, all resources associated with an exchange relay are reclaimed in a timely manner.

[0049] In certain embodiments, a distributed switch may be implemented in a FC environment and may be referred to as a distributed FC switch. In other embodiments the distributed switch may be implemented in an FCoE environment and the distributed switch may be referred to as a distributed FCoE switch. Cascaded switch environments may be generated with distributed FC or FCoE switches, and embodiments that are similar may be implemented for FC and FCoE. Additional Embodiment Details

[0050] The described operations may be implemented as a method, apparatus or computer program product using standard programming and/or engineering techniques to produce software, firmware, hardware, or any combination thereof. Accordingly, aspects of the embodiments may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro-code, etc.) or an embodiment combining software and hardware aspects that may all generally be referred to herein as a "circuit," "module" or "system." Furthermore, aspects of the embodiments may take the form of a computer program product embodied in one or more computer readable medium(s) having computer readable program code embodied there.

[0051] Any combination of one or more computer readable medium(s) may be utilized. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. A computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.

[0052] A computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A computer readable signal medium may be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.

[0053] Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

[0054] Computer program code for carrying out operations for aspects of the present invention may be written in any combination of one or more programming languages, including an object oriented programming language such as Java®, Smalltalk, C++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider). Java and all Java-based trademarks and logos are trademarks or registered trademarks of Oracle and/or its affiliates.

[0055] Aspects of the present invention are described below with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions.

[0056] These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.

[0057] These computer program instructions may also be stored in a computer readable medium that can direct a computer, other programmable data processing apparatus, or other devices to function in a particular manner, such that the instructions stored in the computer readable medium produce an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks.

[0058] The computer program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.

[0059] FIG. 6 illustrates a block diagram that shows certain elements that may be included in the switches 102, 104, 106 in accordance with certain embodiments. The system 600 may include a circuitry 602 that may in certain embodiments include at least a processor 604. The system 600 may also include a memory 606 (e.g., a volatile memory device), and storage 608. The storage 608 may include a non-volatile memory device (e.g., EEPROM, ROM, PROM, RAM, DRAM, SRAM, flash, firmware, programmable logic, etc.), magnetic disk drive, optical disk drive, tape drive, etc. The storage 608 may comprise an internal storage device, an attached storage device and/or a network accessible storage device. The system 600 may include a program logic 610 including code 612 that may be loaded into the memory 606 and executed by the processor 604 or circuitry 602. In certain embodiments, the program logic 610 including code 612 may be stored in the storage 608. In certain other embodiments, the program logic 610 may be implemented in the circuitry 602. Therefore, while FIG. 6 shows the program logic 610 separately from the other elements, the program logic 610 may be implemented in the memory 606 and/or the circuitry 602. [0060] Certain embodiments may be directed to a method for deploying computing instruction by a person or automated processing integrating computer-readable code into a computing system, wherein the code in combination with the computing system is enabled to perform the operations of the described embodiments.

[0061] The terms "an embodiment", "embodiment", "embodiments", "the embodiment", "the embodiments", "one or more embodiments", "some embodiments", and "one embodiment" mean "one or more (but not all) embodiments of the present invention(s)" unless expressly specified otherwise.

[0062] The terms "including", "comprising", "having" and variations thereof mean "including but not limited to", unless expressly specified otherwise.

[0063] The enumerated listing of items does not imply that any or all of the items are mutually exclusive, unless expressly specified otherwise.

[0064] The terms "a", "an" and "the" mean "one or more", unless expressly specified otherwise.

[0065] Devices that are in communication with each other need not be in continuous communication with each other, unless expressly specified otherwise. In addition, devices that are in communication with each other may communicate directly or indirectly through one or more intermediaries.

[0066] A description of an embodiment with several components in communication with each other does not imply that all such components are required. On the contrary a variety of optional components are described to illustrate the wide variety of possible embodiments of the present invention.

[0067] Further, although process steps, method steps, algorithms or the like may be described in a sequential order, such processes, methods and algorithms may be configured to work in alternate orders. In other words, any sequence or order of steps that may be described does not necessarily indicate a requirement that the steps be performed in that order. The steps of processes described herein may be performed in any order practical. Further, some steps may be performed simultaneously.

[0068] When a single device or article is described herein, it will be readily apparent that more than one device/article (whether or not they cooperate) may be used in place of a single device/article. Similarly, where more than one device or article is described herein (whether or not they cooperate), it will be readily apparent that a single device/article may be used in place of the more than one device or article or a different number of devices/articles may be used instead of the shown number of devices or programs. The functionality and/or the features of a device may be alternatively embodied by one or more other devices which are not explicitly described as having such functionality/features. Thus, other embodiments of the present invention need not include the device itself.

[0069] At least certain operations that may have been illustrated in the figures show certain events occurring in a certain order. In alternative embodiments, certain operations may be performed in a different order, modified or removed. Moreover, steps may be added to the above described logic and still conform to the described embodiments. Further, operations described herein may occur sequentially or certain operations may be processed in parallel. Yet further, operations may be performed by a single processing unit or by distributed processing units.

[0070] The foregoing description of various embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto. The above specification, examples and data provide a complete description of the manufacture and use of the composition of the invention. Since many embodiments of the invention can be made without departing from the scope of the invention, the invention resides in the claims hereinafter appended.