FIELD OF THE INVENTION

[00011 The present embodiments of the invention relate generally to phase

interpolators and, more specifically, relate to such interpolators useful in

recovering a clock from serial data sent to a receiver.

BACKGROUND

[0002] In many data communication arrangements, separate clock signals

are not transmitted with the data. This requires recovering the clock from the

data at the receiving end in order to then recover the data. When transmitting the

clocked data across a transmission medium, noise in the data signal, such as jitter

and phase skew, reduces the sampling window for the data. Duty cycle

distortion, for instance, is caused by non-symmetric positive and negative duty

cycles of a data symbol and can show up either as a high frequency correlated

jitter or as a phase step. The jitter, phase skew, and duty cycle distortion reduce

the perceived sampling window by the receiver.

|0003| Phase interpolator circuits are increasingly used in embedded clock

data recovery systems to position the sampling clock at the center of the data eye.

Phase interpolators typically use fixed phase clocks, generated from a Phase

Locked Loop (PLL), and mix them appropriately to generate interpolated clocks

that can be adjusted to be at the center of the data bit. Some implementations of

phase interpolator circuitry contain pre-conditioner circuitry, mixer circuitry, and

an amplifier. With the phase interpolator operating at multiple Gb/S speeds, any

duty cycle corruption can result in improperly sampled data.

[0004] The fixed phase clocks at the input of the phase interpolator may

have some cycle-cycle jitter from the source and power supply noise. There is

also a possibility of phase skew between the adjacent clocks that are mixed in the

phase interpolator. This jitter and phase skew lead to duty cycle distortion in

phase interpolator outputs.

[0005] A conventional phase interpolator circuit is very sensitive to input

jitter and layout mismatches which may result in poor quality clocks. With jitter

and phase skew in the input clocks, the outputs of the pre-conditioner circuitry in

a phase interpolator may have different common mode voltages. These different

common mode voltages cause differing operating points in the differential mixer

circuitry of the phase interpolator. This may result in duty cycle distortion in the

phase interpolator output clocks and, consequently, improperly sampled data.

With higher speeds and jitter associated with clocks increasing, a phase

interpolator that can provide cleaner clocks, even with significant phase skew and

power supply noise induced jitter on the input clocks, will help reduce the

occurrence of improperly sampled data.

BRIEF DESCRIPTION OF THE DRAWINGS

[0006| The present invention will be understood more fully from the

detailed description given below and from the accompanying drawings of various

embodiments of the invention. The drawings, however, should not be taken to

limit the invention to the specific embodiments, but are for explanation and

understanding only.

[0007| Figure 1 illustrates a block diagram of a simple communication

system;

[0008] Figure 2 illustrates a block diagram of a receiver of the type in which

a phase interpolator may be used;

|0009] Figure 3 illustrates a block diagram of one embodiment of a phase

interpolator;

fOOlO] Figure 4 illustrates a graphical representation of ideal phase spacing

of outputs of the phase interpolator;

10011] Figure 5 illustrates a graphical representation of non-ideal phase

spacing of outputs of the phase interpolator;

[0012] Figure 6 illustrates a circuit/block diagram of one embodiment of a

phase interpolator; and

[0013] Figure 7 is a flow diagram of one embodiment of a method for

recovering an embedded clock from a data stream.

DETAILED DESCRIPTION

[0014J A method and apparatus to reduce duty cycle distortion in a phase

interpolator circuit is described. Reference in the specification to "one

embodiment" or "an embodiment" means that a particular feature, structure, or

characteristic described in connection with the embodiment is included in at least

one embodiment of the invention. The appearances of the phrase "in one

embodiment" in various places in the specification are not necessarily all referring

to the same embodiment.

[0015] In the following description, numerous details are set forth. It will

be apparent, however, to one skilled in the art, that the embodiments of the

invention may be practiced without these specific details. In other instances, well-

known structures and devices are shown in block diagram form, rather than in

detail, in order to avoid obscuring the present invention.

[00161 Figure 1 is a block diagram of one embodiment of a simple

communication system 100 that may be used to reduce duty cycle distortion in a

phase interpolator circuit. The system 100 includes a transmitter (Tx) 110, a serial

data signal 130, and a receiver (Rx) 120. Receiver unit 120 further includes a clock

and data recovery (CDR) unit 125.

[0017] Transmitter 102 transmits the serial data signal 130 including, for

example, a series of data symbols, to receiver 120. CDR unit 125 of receiver 120

samples serial data signal 130 (for example, symbols included in the serial data

signal) to recover data from the serial data signal. CDR unit 125 samples serial

data signal 130 at sample times established by a sampling signal 140 generated

locally at receiver 120. In some embodiments, sampling signal 140 may be

generated by a Phase Locked Loop (PLL).

[0018] In recovering data from the serial data signal 130, sampling signal

140 causes CDR unit 125 to sample the serial data signal at sample times

coinciding with occurrences of a maximum Signal-to-Noise (S/N) level of the

serial data signal. Often, however, there is a phase offset between the serial data

signal and the sample signal, causing CDR unit 125 to sample serial data signal

130 at sub-optimal sample times, which can cause errors in recovering the data

from serial data signal 130.

[0019| Figure 2 is a block diagram of one embodiment of a CDR unit 125 of

receiver 120 in which embodiments of a phase interpolator may be used. Remote

serial data on line 210 is input to a phase detect circuit 220, which has as a second

input the recovered remote clock signal on line 290. A control signal from block

220, which represents the difference in phase, is an input to a remote clock

recovery mechanism 230, having as a second input a local reference clock on line

260. Local clock reference on line 260 may be the sampling signal 140 of Figure 1.

[0020] The control signal from block 220 is used to vary the phase of the

recovered remote clock until it is in a desired frequency and phase relationship

with the incoming data. The recovered clock on line 290 is provided as an output

and is used as a clock input to flip-flop 240 that is used to recover the data.

[0021] Figure 3 is a block diagram of one embodiment of a phase

interpolator. The phase interpolator 300 can be used as the remote clock recovery

mechanism 230 in a system such as that of Figure 2. However, the phase

interpolator implementation in Figure 3 is useful in any arrangement where

interpolation between different clock phases is desired.

100221 In the illustrated embodiment, the phase interpolator 300 includes

three circuitry units: a pre-conditioner 310, a mixer 320, and an amplifier 330.

Fixed phase clocks from a Phase Locked Loop (PLL) 350 are used as input clocks

to the pre-conditioner 310. These fixed phase clocks are converted to triangle

waves by the pre-conditioner 310. The pre-conditioner 310 is a square-to-triangle

waveform shaper, which generates good overlap between the two phases. The

output of the pre-conditioner 310 is a resistor-capacitor (RC) type of waveform

rather than a triangle. This basically provides a good region of overlap between

any two adjacent pre-conditioner output phases. The two output phases of the

pre-conditioner are coupled to a common mode circuit 360.

[0023] Common mode circuit 360 contains circuitry to keep the pre-

conditioner outputs biased at the same voltage. It forces the common mode of the

pre-conditioner outputs to be the same, and consequently helps the pre-

conditioner output signals swing around a fixed common mode to produce good

differential signal crossovers and ideal clock outputs. Implementing the common

mode circuit 360 may help produce proper phase spacing of the phase

interpolator outputs after amplification. The output of the common mode circuit

360 is coupled to a mixer circuit 320.

[0024] At mixer circuit 320, the signal phases outputted from the pre-

conditioner 310 are mixed proportionately based on proportionate current

weighing. The mixer 320 takes in any of the plurality of adjacent triangular waves

and mixes them to produce a resultant output that is close to sinusoidal in shape.

The output of the mixer is controlled to produce an output whose phase is

somewhere between the mixer input phases.

[0025] The proportionate current weighting implemented in the mixer

circuit is controlled by a Digital-to- Analog Converter (DAC) 340. The DAC 240

controls are generated based on edge and data samples, as well as the current

position of the sampling clock. Proportional weighting of currents between IQl

and IQ2, illustrated in Figure 3, determines the output phase. The sum of the

currents IQl and IQ2 is constant, K.

[0026] The output of the mixer 320 is analog and is fed to another common

mode circuit 370. Common mode circuit 370 operates analogously to common

mode circuit 360 to facilitate proper phase spacing of the outputs of mixer 320.

Embodiments of the present invention may not require both common mode

circuits 360 and 370. Some embodiments may implement only one of these

common mode circuits, while other embodiments may implement both common

mode circuits.

[0027] The output of the common mode circuit 370 is fed to an amplifier

330 that produces rail to rail (OV to VDD voltage swing) sampling clocks.

Amplifier 330 may in some embodiments be a CMOS (Complementary Metal

Oxide Semiconductor) level converter.

[0028] Figures 4 and 5 are graphical illustrations of phase spacing within

the phase interpolator at each of the pre-conditioner 310 input, pre-conditioner

310 output, mixer 320 output, and phase interpolator output (i.e., amplifier 330

output). The pre-conditioner 310 input clocks that come out of the PLL 350 are

routed several thousand microns and buffered periodically before they go to each

phase interpolator in a multi-lane configuration. Generally, these fixed phase

clocks at the input of pre-conditioner will have some cycle-cycle jitter from the

source and power supply noise. There is also a possibility of phase skew between

the adjacent clocks that are mixed.

[0029] Figure 4 illustrates ideal phase spacing within the phase interpolator

when there is no jitter or phase skew present in the input clocks to the phase

interpolator. Phase spacing at each of the pre-conditioner input, pre-conditioner

output, mixer output, and the phase interpolator output (amplifier output) is

shown. Ideally, the phase spacing between two adjacent output phases is T/n pS,

where T is the period in Pico seconds and n is the number of input phases within

each period. For example, the phase spacing between Phase 1 and Phase 2, and

Phase 2 and Phase 3, and Phase 3 and Phase 4, and Phase 4 and Phase 1, in an

ideal 4-phase system will be T/4 pS.

[0030] In Figure 4, line (a) depicts ideal pre-conditioner input phase

spacing. Line (b) depicts the resulting phase spacing at the pre-conditioner

output. Line (c) depicts the resulting mixer output phase spacing. Line (d)

depicts the overall phase spacing at the phase interpolator output (at the

amplifier).

|0031] Figure 5 graphically depicts non-ideal phase spacing within the

phase interpolator. Such a non-ideal scenario may occur when there is jitter

and/or phase skew present in the input clocks to the phase interpolator. In

general, the common mode and signal swing of the pre-conditioner outputs

determine the bias point of the mixer outputs. The bias point of the mixer outputs

is the pseudo common mode of the differential swings at the output of the mixer.

As the pre-conditioner clocks are displaced in time due to jitter and skew, the

outputs of the pre-conditioner can have different common modes. The different

common modes at the pre-conditioner outputs may bias the mixer outputs to

different voltage levels.

[0032] Furthermore, different common modes may cause mixer crossovers

to be significantly different from expected values and result in long pulse-short

pulse scenarios, thereby leading to duty cycle distortion in the phase interpolator

outputs. With phase skews in the pre-conditioner input clocks, the pre-

conditioner outputs swing around different common modes causing shifting of

mixer output bias voltages. With phase skews (time) present, mixer output bias

skews (voltage) result, leaving bad duty cycle clocks. In other words, poor phase

spacing of the output clocks results. Figure 5 illustrates the effect of non-ideal

phase spacing of the pre-conditioner input clocks on the phase interpolator

output.

10033] In Figure 5, line (a) depicts non-ideal pre-conditioner input phase

spacing. Line (b) depicts the resulting phase spacing at the pre-conditioner

output. Line (c) depicts the resulting mixer output phase spacing with skewed

bias points. Line (d) depicts the overall phase spacing at the phase interpolator

output (at the amplifier) with duty cycle distortion.

[0034J Figure 6 illustrates a circuit/block diagram of one embodiment of a

phase interpolator, such as phase interpolator 300 of Figure 3, used to alleviate the

duty cycle distortion in the phase interpolator circuit. The diagram includes

circuit level implementation of the pre-conditiυner 310, the mixer 320, the

amplifier 330, and the common mode circuits 360, 370, as depicted in Figure 3.

[0035] The common mode circuits 360, 370 include an alternating current

(AC) coupling capacitor 610, 630, together with a common mode bias keeper

circuit 620, 640. AC coupling capacitor 610, 630 and common mode bias keeper

circuit 620, 640 operate together to maintain the common mode of the input

signals to the common mode circuit 360, 370.

[0036] A common mode circuit 360 may be located between the pre-

conditioner circuitry 310 and the mixer circuitry 320. Alternatively, in other

embodiments, common mode circuit 370 may be located between the mixer

circuitry 320 and the amplifier 330. One embodiment of the phase interpolator

may include both common mode circuit 370 between the mixer circuitry 320 and

the amplifier 330, and common mode circuit 360 between the pre-conditioner

circuitry 310 and the mixer circuitry 320.

[0037] The embodiment of phase interpolator 300 presented in Figure 6

may lessen differences in common mode bias voltages at the differential outputs

of the mixer 32O ₇ keeping both outputs biased at the same voltage and thereby

producing proper phase spacing after amplification. The embodiment of phase

interpolator 300 also forces the common mode of the differential outputs of the

pre-conditioner 310 to be one value and the common mode at the mixer 320

outputs to be the same. Consequently, the signals swing around a fixed common

mode, thereby producing good differential signal crossovers and ideal clock

outputs of the phase interpolator 300.

[0038] Figure 7 is a flow diagram illustrating one embodiment of a method

700 for recovering an embedded clock from a data stream. Recovering the

embedded clock from the data stream includes the phase interpolator maintaining

the common mode of the signals it is processing. The flow diagram includes, at

process block 710, receiving a plurality of reference clock signals. Process block

720 includes maintaining a common mode of the plurality of reference clock

signals by a common mode circuit, the common mode circuit including an AC

capacitor and a common mode bias keeper circuit. Next, process block 730

includes generating interrelated control signals based on comparing the plurality

of reference clocks to a received data signal. Lastly, process block 740 includes

outputting amplitude contributions from phases of the interrelated control

signals.

[0039] Method 700 may be implemented in the embodiments of phase

interpolator illustrated in Figures 3 and 6. More specifically, maintaining a

common mode of the plurality of reference clock signals at process block 720, may

be implemented with common mode circuits 360 and 370 as depicted in Figures 3

and 6. Furthermore, the maintaining of a common mode of the plurality of

reference clock signals further includes forcing the common mode of the plurality

of reference clock signals to be the same.

[0040] Embodiments of the phase interpolator and its accompanying data

recovery scheme may be used in serial interfaces such as PCI Express. However,

the embodiments of the phase interpolator implementation presented here are

useful in any arrangement where serial data transfer over a networks system is

desired.

[0041] Whereas many alterations and modifications of the present

invention will no doubt become apparent to a person of ordinary skill in the art

after having read the foregoing description, it is to be understood that any

particular embodiment shown and described by way of illustration is in no way

intended to be considered limiting. Therefore, references to details of various

embodiments are not intended to limit the scope of the claims, which in

themselves recite only those features regarded as the invention.