Title:
MEMORY ACCESS DEVICE
Document Type and Number:
WIPO Patent Application WO/2006/046272
Kind Code:
A1
Abstract:
An equipment using a device for having access to a memory such as CPU is equipped with a memory access device for realizing a high-speed memory access without using a cache and for a memory having no high-speed access mode. In this memory access device, a write unit (211) accepts, in response to a first write instruction from the CPU (1), a first write address and first write data from a single buffer (22), to send a write complete signal (2a) to the CPU (1) irrespective of whether or not the writing operation has been completed, while executing the writing operation in real time. A read unit (212) accepts, in response to a first read instruction from the CPU (1), a first read address from the CPU (1), to execute the read operation in real time, and accepts first read data from a memory (3), to send the read data and a read complete signal (2b) to the CPU (1).
Inventors:
ONISHI TAKAYUKI (JP)
Application Number:
PCT/JP2004/014722
Publication Date:
May 04, 2006
Filing Date:
October 06, 2004
Export Citation:
Assignee:
MITSUBISHI ELECTRIC CORP (JP)
ONISHI TAKAYUKI (JP)
ONISHI TAKAYUKI (JP)
International Classes:
G06F12/00; (IPC1-7): G06F12/00
Foreign References:
| JPS61168058A | 1986-07-29 | |||
| JPH09505679A | 1997-06-03 | |||
| JP2004199608A | 2004-07-15 | |||
| JPH03263156A | 1991-11-22 | |||
| JPH06175911A | 1994-06-24 |
Attorney, Agent or Firm:
Takahashi, Shogo c/o Mitsubishi Denki Kabushiki kaisha Corporate Intellectual Property Division (7-3 Marunouchi 2-chome, Chiyoda-k, Tokyo ., JP)
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