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Patent Searching and Data


Title:
MEMORY ARCHITECTURE AND OPERATION
Document Type and Number:
WIPO Patent Application WO/2019/041082
Kind Code:
A1
Abstract:
Methods include programming a first portion of memory cells of a string of series-connected memory cells closer to a particular end of the string than a second portion of memory cells of the string in an order from a different end of the string to the particular end, and programming the second portion of memory cells in an order from the particular end to the different end. Methods further include incrementing a first read count and a second read count in response to performing a read operation on a memory cell of a block of memory cells, resetting the first read count in response to performing an erase operation on a first portion of memory cells of the block of memory cells, and resetting the second read count in response to performing an erase operation on the second portion of memory cells of the block of memory cells.

Inventors:
LIANG, Ke (Room 701, RD Chunquan Lane 45, No 31, Shanghai 0, 201210, CN)
XU, Jun (No. 102, Lane 133 Shangwen Road, Shanghai 10, 2000010, CN)
Application Number:
CN2017/099234
Publication Date:
March 07, 2019
Filing Date:
August 28, 2017
Export Citation:
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Assignee:
MICRON TECHNOLOGY, INC. (P.O.Box 6, 8000 South Federal WayBoise, Idaho, 83716, US)
International Classes:
G11C11/34
Foreign References:
US20090129152A12009-05-21
US8737131B22014-05-27
CN106297880A2017-01-04
CN106449644A2017-02-22
Attorney, Agent or Firm:
LEE AND LI - LEAVEN IPR AGENCY LTD. (Unit 2202, Tower A Beijing Marriott Center,No. 7, Jianguomen South Avenue, Beijing 5, 100005, CN)
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