MEMORY CELL, MEMORY CELL ARRANGEMENT, STRUCTURING ARRANGEMENT AND METHOD FOR PRODUCTION OF A MEMORY CELL

WIPO Patent Application WO2004040644

A3

The invention relates to a memory cell, memory cell arrangement, structuring arrangement and method for production of a memory cell. The memory cell has a vertical gate transistor and a memory capacitor, whereby the vertical gate transistor comprises a semiconducting nanostructure, grown on at least part of the memory capacitor.

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GRAHAM ANDREW (DE)
HOFMANN FRANZ (DE)
HOENLEIN WOLFGANG (DE)
KRETZ JOHANNES (DE)
KREUPL FRANZ (DE)
LANDGRAF ERHARD (DE)
LUYKEN RICHARD JOHANNES (DE)
ROESNER WOLFGANG (DE)
SCHULZ THOMAS (DE)
SPECHT MICHAEL (DE)

PCT/DE2003/003589

August 12, 2004

October 29, 2003

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INFINEON TECHNOLOGIES AG (DE)
GRAHAM ANDREW (DE)
HOFMANN FRANZ (DE)
HOENLEIN WOLFGANG (DE)
KRETZ JOHANNES (DE)
KREUPL FRANZ (DE)
LANDGRAF ERHARD (DE)
LUYKEN RICHARD JOHANNES (DE)
ROESNER WOLFGANG (DE)
SCHULZ THOMAS (DE)
SPECHT MICHAEL (DE)

G11C13/02; H01L21/8242; H01L27/108; H01L51/00; H01L51/05; H01L51/30; (IPC1-7): H01L21/8239; H01L21/8242; H01L27/108; H01L51/20

WO2003050854A2	2003-06-19
WO2001057917A2	2001-08-09

US20020001905A1	2002-01-03
US5256588A	1993-10-26
US20010021553A1	2001-09-13
DE10118405A1	2002-10-24
US5610441A	1997-03-11

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