Title:
MEMORY CELL ARRAY UNIT
Document Type and Number:
WIPO Patent Application WO/2022/085471
Kind Code:
A1
Abstract:
A memory cell array unit according to one embodiment of the present disclosure comprises a memory cell array and a microcontroller. The memory cell array is configured by including: n assignment bits to be assigned from the memory controller in reading/writing control; and one or more redundant bits which are not provided with switching mechanisms for switching as alternatives to some of the assignment bits. The microcontroller reads/writes data of n bits from/in the memory cell array by using the assignment bits and the redundant bits on the basis of the reading/writing control from the memory control.
Inventors:
SAKAI LUI (JP)
KANDA YASUO (JP)
KANDA YASUO (JP)
Application Number:
PCT/JP2021/037181
Publication Date:
April 28, 2022
Filing Date:
October 07, 2021
Export Citation:
Assignee:
SONY SEMICONDUCTOR SOLUTIONS CORP (JP)
International Classes:
H01L45/00; G06F11/16; G11C29/00; H01L21/8239; H01L27/105; H01L49/00
Foreign References:
| JP2010282725A | 2010-12-16 | |||
| JP2015121944A | 2015-07-02 | |||
| JP2010146654A | 2010-07-01 |
Attorney, Agent or Firm:
TSUBASA PATENT PROFESSIONAL CORPORATION (JP)
Download PDF: