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Patent Searching and Data


Title:
MEMORY CELL CAPACITOR PLATE
Document Type and Number:
WIPO Patent Application WO/2000/059011
Kind Code:
A2
Abstract:
An improved method of forming a memory cell capacitor plate is disclosed. The method of forming a memory cell capacitor plate comprises the steps of depositing a sacrificial layer and forming an opening in the sacrificial layer. Then an electrode material layer which includes a substantially conductive material that remains substantially conductive upon exposure to oxygen is deposited over a top surface of the sacrificial layer and at least partially filling the opening. The method continues with removing a portion of the electrode material layer down to at least about a level of the sacrificial layer's top surface to define a top surface of the memory cell capacitor plate, followed by removal of the sacrificial layer.

Inventors:
Keil, Douglas L. (34421 Montgomery Place Fremont, CA, 94555, US)
Application Number:
PCT/US2000/008638
Publication Date:
October 05, 2000
Filing Date:
March 30, 2000
Export Citation:
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Assignee:
LAM RESEARCH CORPORATION (4650 Cushing Parkway Fremont, CA, 94538-6516, US)
International Classes:
H01L21/3205; H01L21/02; H01L21/768; H01L21/8242; H01L27/108; (IPC1-7): H01L21/02
Foreign References:
US5808854A1998-09-15
US5392189A1995-02-21
US5366920A1994-11-22
US5789320A1998-08-04
EP0834912A21998-04-08
US5283201A1994-02-01
US5801916A1998-09-01
Attorney, Agent or Firm:
Lee, Michael (Beyer Weaver Thomas & Nguyen, LLP P.O. Box 130 Mountain View, CA, 94042-0130, US)
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Claims:
What is claimed is:
1. A method of forming a memory cell capacitor plate. comprising: depositing a sacrificial layer; forming an opening in said sacrificial layer; depositing an electrode material layer over a top surface of said sacrificial layer and at least partially filling said opening, wherein said electrode material layer includes a substantially conductive material that remains substantially conductive upon exposure to oxygen; removing a portion of said electrode material layer down to at least about a level of said top surface of said sacrificial layer to define a top surface of said memory cell capacitor plate; and removing said sacrificial layer.
2. The method of claim 1, wherein said electrode material layer includes platinum.
3. The method of claim 1, wherein said electrode material layer includes one of ruthenium, ruthenium oxide, iridium, and iridium oxide.
4. The method of claim 1, wherein said top surface of said memory cell capacitor plate has a plurality of sharp corners, further comprising: rounding said plurality of said sharp corners of said memory cell capacitor plate.
5. The method of claim 4, wherein said rounding of said plurality of said sharp corners of said memory cell capacitor plate is achieved by a sputtering process.
6. The method of claim 4, wherein said rounding of said plurality of said sharp corners of said memory cell capacitor plate is achieved by a plasma etching process.
7. The method of claim 4. wherein a process used to achieve said rounding of said plurality of said sharp corners of said memory cell capacitor plate also effects said removing of said sacrificiallayer.
8. A method of forming a memory cell capacitor. comprising forming a first capacitor plate using the method of claim 1; forming a storage element over said first capacitor plate: and forming a second capacitor plate over said storage element.
9. The method of claim 8. wherein said storage element is formed by the method of claim 1. wherein said memory cell capacitor plate is replaced by said storage element, wherein said electrode material layer is replaced by a dielectric layer, and wherein said storage element maintains electrical contact with said first capacitor plate.
10. The method of claim 8, wherein said storage element is formed by conformal deposition of a dielectric layer.
11. The method of claim 8, wherein said storage element includes a ferroelectric material.
12. The method of claim 8, wherein said second capacitor plate is formed by the method of claim 1 and wherein said forming of said second capacitor plate maintains electrical contact with said storage element.
13. The method of claim 8, wherein said second capacitor plate is formed by conformal deposition of an electrode material layer.
14. The method of claim 8, wherein said second capacitor plate includes one of platinum. ruthenium, ruthenium oxide, iridium, and iridium oxide.
15. The method of claim 8, further comprising: depositing an encapsulating material layer over said memory cell capacitor.
16. The method of claim 1, wherein said memory cell capacitor plate is disposed above a substrate.
17. The method of claim 16. further comprising: depositing a boundary layer over said substrate.
18. The method of claim 17, wherein said boundary layer functions as an etch stop layer.
19. The method of claim 17. wherein said boundary layer functions as a diffusion barrier layer.
20. The method of claim 17, wherein said boundary layer includes one of titanium nitride and silicon nitride.
21. The method of claim 16, wherein said substrate has a conductive plug, said conductive plug being surrounded by insulating material.
22. The method of claim 1, wherein said sacrificial layer is an oxide layer. <BR> <BR> <BR> <BR> <BR> <BR> <BR> <P>23. The method of claim 1.
23. wherein said removing of said portion of said electrode material layer is accomplished by a planarizing process.
24. The method of claim 23, wherein said planarizing process is a chemical mechanical polishing (CMP) process.
25. The method of claim 1. wherein said capacitor plate is employed in the fabrication of a SmartCard.
26. The method of claim 1, wherein said capacitor plate is employed in the fabrication of a DRAM.
27. A method of forming a platinumcontaining memory cell capacitor plate. comprising: depositing a sacrificial layer ; forming an opening in said sacrificial layer; depositing a platinumcontaining layer over a top surface of said sacrificial layer and at least partially filling said opening : removing a portion of said platinumcontaining layer down to at least about a level of said top surface of said sacrificial layer to define a top surface of said platinumcontaining memory cell capacitor plate ; and removing said sacrificial layer.
28. The method of claim 27, wherein said top surface of said platinumcontaining memory cell capacitor plate has a plurality of sharp corners. further comprising: rounding said plurality of said sharp corners of said platinumcontaining memory cell capacitor plate.
29. The method of claim 28, wherein said rounding of said plurality of said sharp corners of said platinumcontaining memory cell capacitor plate is achieved by a sputtering process.
30. The method of claim 28, wherein said rounding of said plurality of said sharp corners of said platinumcontaining memory cell capacitor plate is achieved by a plasma etching process.
31. The method of claim 28, wherein a process used to achieve said rounding of said plurality of said sharp corners also effects said removing of said sacrificial layer.
32. A method of forming a memory cell capacitor, comprising forming a first platinumcontaining capacitor plate using the method of claim 27 : forming a storage element over said first platinumcontaining capacitor plate; and forming a second platinumcontaining capacitor plate over said storage element.
33. The method of claim 31, wherein said storage element is formed by the method of claim 27, wherein said memory cell capacitor plate is replaced by said storage element, wherein said platinumcontaining layer is replaced by a dielectric layer, and wherein said storage element maintains electrical contact with said first capacitor plate.
34. The method of claim 31. wherein said storage element is formed by conformal deposition of a dielectric laver.
35. The method of claim 31. wherein said storage element includes a ferroelectric material.
36. The method of claim 31. wherein said second platinumcontaining capacitor plate is formed by the method of claim 27. and wherein said second platinumcontaining capacitor plate maintains electrical contact with said storage element.
37. The method of claim 31, wherein said second platinumcontaining capacitor plate is formed by conformal deposition of a platinumcontaining layer.
38. The method of claim 31. further comprising: depositing an encapsulating material layer over said memory cell capacitor.
39. The method of claim 27. wherein said platinumcontaining memory cell capacitor plate is disposed above a substrate.
40. The method of claim 39, further comprising: depositing a boundary layer over said substrate.
41. The method of claim 40, wherein said boundary layer functions as an etch stop layer.
42. The method of claim 40, wherein said boundary layer functions as a diffusion barrier layer.
43. The method of claim 40, wherein said boundary layer includes one of titanium nitride and silicon nitride.
44. The method of claim 39, wherein said substrate has a conductive plug, said conductive plug being surrounded by insulating material.
45. The method of claim 27. wherein said sacrificial layer is an oxide layer.
46. The method of claim 27. wherein said removing of said portion of said electrode material layer is accomplished by a planarizing process.
47. The method of claim 46. wherein said planarizing process is a chemical mechanical polishing (CMP) process.
48. The method of claim 27. wherein said capacitor plate is employed in the fabrication of a SmartCard.
49. The method of claim 27, wherein said capacitor plate is employed in the fabrication of a DRAM.
50. A method of forming a memory cell capacitor structure, comprising: depositing a first sacrificial layer; forming a first opening in said first sacrificial layer : depositing a first electrode material layer over a top surface of said first sacrificial layer and at least partially filling said first opening, wherein said first electrode material layer includes a substantially conductive material that remains substantially conductive upon exposure to oxygen; removing a portion of said first electrode material layer over down to at least about a level of said top surface of said first sacrificial layer to define a top surface of a first memory cell capacitor plate; depositing a second sacrificial layer; forming a second opening in said second sacrificial layer; depositing a dielectric layer over a top surface of said second sacrificial layer and at least partially filling said second opening, said dielectric layer having electrical contact with said first memory cell capacitor plate; removing a portion of said dielectric layer over down to at least about a level of said top surface of said second sacrificial layer to define a top surface of a memory cell capacitor storage element; removing said second sacrificial layer ; removing said first sacrificial layer; and forming a second memory cell capacitor plate over said memory cell capacitor storage element.
51. The method of 50* wherein said substantially oxygen resistant conducting material is one of platinum. ruthenium. ruthenium oxide, iridium. and iridium oxide. C1.2 The method of 50. wherein said dielectric laver includes a ferroelectric material.
52. The method of claim 50* wherein said second memory cell capacitor plate is formed by conformally depositing a second electrode material layer over said memory cell capacitor storage element, said second electrode material layer including a substantially oxygen resistant conducting material.
53. The method of claim 50, wherein said forming of said second memory cell capacitor plate takes place prior to said removing of said first and said second sacrificial layers, said forming of said second memory cell capacitor plate including: depositing a third sacrificial layer; forming a third opening in said third sacrificial layer; depositing a second electrode material layer over a top surface of said third sacrificial layer and at least partially filling said third opening, said second electrode material layer including a substantially conductive material that remains substantially conductive upon exposure to oxygen, and said second electrode material layer having electrical contact with said memory cell capacitor storage element; removing a portion of said second electrode material layer over down to at least about a level of said top surface of said third sacrificial layer to define a top surface of said second memory cell capacitor plate; and removing said third sacrificial layer.
54. The method of claim 50, wherein said top surface of said first memory cell capacitor plate has a plurality of sharp corners, further comprising: rounding said plurality of said sharp corners of said first memory cell capacitor plate.
55. The method of claim 54. wherein said rounding of said plurality of said sharp corners of said first memory cell capacitor plate is achieved by a sputtering process.
56. The method of claim 54. wherein said rounding of said plurality of said sharp corners of said first memory cell capacitor plate is achieved by a plasma etching process. 57. The method of claim 54.
57. wherein a process used to achieve said rounding of said plurality of said sharp corners of said first memory cell capacitor plate also effects said removing of said first sacrificial layer.
58. The method of claim 50, wherein said memory cell capacitor structure is employed in the fabrication of a SmartCard.
59. The method of claim 50, wherein said memory cell capacitor structure is employed in the fabrication of a DRAM.
60. The method of claim 50, further comprising: depositing an encapsulating material layer over said memory cell capacitor structure.
61. The method of claim 50, wherein said memory cell capacitor structure is disposed above a substrate.
62. The method of claim 61. further comprising: depositing a boundary layer over said substrate.
63. The method of claim 62, wherein said boundary layer functions as an etch stop layer.
64. The method of claim 62, wherein said boundary layer functions as a diffusion barrier layer.
65. The method of claim 62, wherein said boundary layer includes one of titanium nitride and silicon nitride.
66. The method of claim 50, wherein said removing of said portion of said electrode material layer is accomplished by a planarizing process.
67. The method of claim 66. wherein said planarizing process is a chemical mechanical polishing (CMP) process.
Description:
INTERNATIONAL SEARCH REPORT Inter, onal Application No PCT/US 00/08638 C. (Continuation) DOCUMENTS CONSiDERED TO BE RELEVANT Category ciiaîion of documenî. with indication, where appropriate, of the relevant passages Relevant to claim No. X US 5 392 189 A (FAZAN PIERRE C ET AL) 1-3,8, 21 February 1995 (1995-02-21) 10, 11. 13,14, 16,17, 19-27, 32,34, 35,37. 39,40, 42-49 A 4-7, 9, 12, 28-31, 33,36 column 6, line 43-column 8, line 64 figures 13A, 15A X US 5 366 920 A (HASHIMOTO TOSHIKI ET AL) 1,2,8, 22 November 1994 (1994-11-22) 10, 13, 15-23, 25-27 A4-7,9, 11,12, 28-31 column 4, line 30-column 6, line 43 figures 3A-3H, 6A-6H, 7A-7H X US 5 789 320 A (SCHROTT ALEJANDRO GABRIEL 1-3, ET AL) 4 August 1998 (1998-08-04) 25-27, 32-35, 39-41, 43,44, 46-49 A 4-11, 13-15, 17,18, 20-24, 28-31, 36,37 column 5, line 56-column 7, line 64 column 9, line 35-line 67 figures 3F-3K A EP 0 834 912 A (TEXAS INSTRUMENTS INC) 50-59, 8 April 1998 (1998-04-08) 61-67 column 13, line 3-column 15, line 43 figures 13-20 A US 5 283 201 A (PIKE JR DOUGLAS A ET AL) 50-59, 1 February 1994 (1994-02-01) 62-67 column 5, line 59-column 7, line 31 figures 7-9 2 INTERNATIONAL SEARCH REPORT Inter, onal Application No PCT/US 00/08638 C. (Continuation) DOCUMENTS CONSIDERED TO BE RELEVANT Category'Citation of document, with indication, where appropriate, of the relevant passages Relevant to claim No. A US 5 801 916 A (NEW DARYL C) 50-59, 1 September 1998 (1998-09-01) 61-67 column 5, line 27-column 7, line 41 figures 3-5 2 International application No. INTERNATIONAL SEARCH REPORT PCT/US 00/08638 Box I Observations where certain claims were found unsearchable (Continuation of item 1 of first sheet) This International Search Report has not been established in respect of certain claims under Article 17 (2) (a) for the following reasons: 1. ClaimsNos.: because they relate to subject matter not required to be searched by this Authority, namely : 2. Claims Nos.: because they relate to parts of the International Apptication that do not comply with the prescribed requirements to such an extent that no meaningful International Search can be carried out, specifically : 3. Claims Nos.: because they are dependent claims and are not drafted in accordance with the second and third sentences of Rule 6.4 (a). Box 11 Observations where unity of invention is lacking (Continuation of item 2 of first sheet) This international Searching Authority found multiple inventions in this international application, as follows : see additional sheet 1. Sa As all required additional search fees were timely paid by the applicant, this International Search Report covers all searchable claims. 2. As all searchable claims could be searched without effort justifying an additional fee, this Authority did not invite payment of any additional fee. 3. As only some of the required additional search fees were timely paid by the applicant, this International Search Report covers only those claims for which fees were paid, specifically claims Nos.: 4. nj No required additional search fees were timely paid by the applicant. Consequently, this International Search Report is restricted to the invention first mentioned in the claims; it is covered by claims Nos.: Remark on Protest The additional search fees were accompanied by the applicant's protest. u X No protest accompanied the payment of additional search fees. LJ International Application No. PCTKJS 00 b8638 FURTHER INFORMATION CONTINUED FROM PCTnSA/210 This International Searching Authority found multiple (groups of) inventions in this international application, as follows: 1. Claims: 1-49 Method for forming a memory cell capacitor with the steps of: Forming a first capacitor plate using the method of: -Depositing a sacrificial layer; -Forming an opening in the sacrificial layer; -Depositing an electrode material that remains conductive upon exposure to oxygen (like a platinum containing layer) to at least filling the opening; -Removing portion of said electrode; -Removing said sacrificial layer. Forming a storage element over the first capacitor plate ; Forming a second capacitor plate. 2. Claims: 50-67 Method for forming a memory cell capacitor with the steps of: -Depositing a first sacrificial layer; -Forming a first opening in said first sacrificial layer; -Depositing a first electrode material that remains conductive upon exposure to oxygen to at least partially filling the opening; -Removing portion of said first electrode; -Depositing a second sacrificial layer; -Forming a second opening in said second sacrificial layer; -Depositing a dielectric layer to at least partially filling said second opening; -Removing portion of said dielectric layer; -Removing said second sacrificial layer; -Removing said first sacrificial layer. -Forming a second capacitor plate. INTERNATIONAL SEARCH REPORT Inter. onal Application No Information on patent family members Patent document Publication Patent family Publication cited in search report date member (s) date US 5808854 A 15-09-1998 US 5559666 A 24-09-1996 US 5464786 A 07-11-1995 US 5654224 A 05-08-1997 US 5392189 A 21-02-1995 US 6066528 A 23-05-2000 US 5381302 A 10-01-1995 US 5506166 A 09-04-1996 US 5478772 A 26-12-1995 US 6030847 A 29-02-2000 US 5959327 A 28-09-1999 US 5366920 A 22-11-1994 JP 2550852 B 06-11-1996 JP 6302764 A 28-10-1994 US 5789320 A 04-08-1998 NONE EP 0834912 A 08-04-1998 JP 10107223 A 24-04-1998 US 5283201 A 01-02-1994 US 4895810 A 23-01-1990 US 5182234 A 26-01-1993 US 5262336 A 16-11-1993 EP 0654173 A 24-05-1995 WO 9403922 A 17-02-1994 US 5801417 A 01-09-1998 US 5648283 A 15-07-1997 AT 144078 T 15-10-1996 CA 1305261 A 14-07-1992 CA 1326567 A 25-01-1994 CA 1326568 A 25-01-1994 DE 68927309 D 14-11-1996 DE 68927309 T 06-03-1997 EP 0342952 A 23-11-1989 JP 2056937 A 26-02-1990 JP 3025277 B 27-03-2000 US 5528058 A 18-06-1996 US 5045903 A 03-09-1991 US 5019522 A 28-05-1991 US 5089434 A 18-02-1992 US 5256583 A 26-10-1993 US 5190885 A 02-03-1993 US 5283202 A 01-02-1994 EP 0601093 A 15-06-1994 JP 6510400 T 17-11-1994 WO 9305535 A 18-03-1993 US 5801916 A 01-09-1998 US 5631804 A 20-05-1997 US 6133108 A 17-10-2000 US 5985676 A 16-11-1999