MEMORY CELL FOR HIGH-DENSITY RRAM DEVICES

WIPO Patent Application WO/2012/141898

A3

This disclosure provides embodiments for the formation of vertical memory cell structures (38) that may be implemented in RRAM devices. In one embodiment, memory cell area may be increased by varying word line (22) height (?WL) and/or word line (22) interface surface (50) characteristics to ensure the creation of a grain boundary that is suitable for formation of conductive pathways through an active layer (44) of an RRAM memory cell (20). This may maintain continuum behavior while reducing random cell-to-cell variability that is often encountered at nanoscopic scales. In another embodiment, such vertical memory cell structures (38) may be formed in multiple-tiers to define a three-dimensional RRAM memory array (110). Further embodiments also provide a spacer pitch-doubled RRAM memory array (120) that integrates vertical memory cell structures (38).

SILLS SCOTT E (US)
SANDHU GURTEJ (US)

PCT/US2012/031004

January 31, 2013

March 28, 2012

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MICRON TECHNOLOGY INC (US)
SILLS SCOTT E (US)
SANDHU GURTEJ (US)

H01L27/24; H01L45/00

US20050040482A1	2005-02-24
US20060105556A1	2006-05-18

CHANG W-Y ET AL: "Unipolar resistive switching characteristics of ZnO thin films for nonvolatile memory applications", APPLIED PHYSICS LETTERS, vol. 92, no. 2, January 2008 (2008-01-01), pages 022110/1 - 3, XP012107012, ISSN: 0003-6951
KANG S-O ET AL: "Layer-to-island growth of electrodeposited Cu2O films and filamentary switching in single-channeled grain boundaries", JOURNAL OF APPLIED PHYSICS, vol. 107, no. 5, March 2010 (2010-03-01), pages 053704/1 - 5, XP012133565, ISSN: 0021-8979

MANWARE, Robert A. et al. (P.O. Box 692289Houston, Texas, US)

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