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Patent Searching and Data


Title:
MEMORY CELL STRUCTURE, MEMORY ARRAY STRUCTURE, SEMICONDUCTOR STRUCTURE, AND MANUFACTURING METHOD THEREFOR
Document Type and Number:
WIPO Patent Application WO/2023/151133
Kind Code:
A1
Abstract:
A memory cell structure, a memory array structure, a semiconductor structure and a manufacturing method therefor. The memory cell structure comprises a substrate, an active region, a word line structure, an insulating dielectric layer and a capacitor structure. A bit line structure is provided in the substrate. The active region is arranged on the bit line structure and comprises, in a direction perpendicular to the substrate, a first connecting terminal, a second connecting terminal away from the first connecting terminal and a channel area located between the first connecting terminal and the second connecting terminal, the first connecting terminal being electrically connected to the bit line structure. The word line structure covers the side wall of a channel region in the direction perpendicular to the substrate. The insulating dielectric layer covers the word line structure and the outer sides of the first connecting terminal and the second connecting terminal. The capacitor structure covers the outer side of the insulating dielectric layer and covers the top surface of the insulating dielectric layer and the top surface of the second connecting terminal, the capacitor structure being electrically connected to the second connecting terminal. In the memory cell structure, an annular channel capacitor structure is utilized to reduce the structural height and increase the memory density.

Inventors:
SHAO GUANGSU (CN)
Application Number:
PCT/CN2022/077731
Publication Date:
August 17, 2023
Filing Date:
February 24, 2022
Export Citation:
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Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
H01L29/786
Foreign References:
CN112997319A2021-06-18
CN113066794A2021-07-02
CN113451312A2021-09-28
US20130069052A12013-03-21
Attorney, Agent or Firm:
ADVANCE CHINA IP LAW OFFICE (CN)
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