Title:
MEMORY CELL STRUCTURE, MEMORY ARRAY STRUCTURE, AND VOLTAGE BIAS METHOD
Document Type and Number:
WIPO Patent Application WO/2021/207916
Kind Code:
A1
Abstract:
The present disclosure provides a memory cell structure, a memory array structure, and a voltage bias method. The memory cell structure comprises: a substrate layer, a well layer, and a transistor. The substrate layer is used for supporting the memory cell structure; the well layer is embedded in the substrate layer, the upper surface of the well layer is flush with the upper surface of the substrate layer, and the transistor is arranged on the well layer. In the present disclosure, deep well bias is performed on the memory cell structure so that a trap voltage of a memory cell can be independently biased into a specific voltage; in conjunction with a redesigned memory cell array structure, most of an applied programming voltage falls on the memory cell structure, thereby reducing the programming voltage of the memory cell, avoiding a gating transistor from being broken down due to an overhigh voltage, and ensuring better reliability of a device and higher area efficiency of the memory cell array structure.
Inventors:
LV HANGBING (CN)
YANG JIANGUO (CN)
XU XIAOXIN (CN)
LIU MING (CN)
YANG JIANGUO (CN)
XU XIAOXIN (CN)
LIU MING (CN)
Application Number:
PCT/CN2020/084621
Publication Date:
October 21, 2021
Filing Date:
April 14, 2020
Export Citation:
Assignee:
INST OF MICROELECTRONICS CAS (CN)
International Classes:
G11C13/00; H01L27/24
Foreign References:
| CN1177211A | 1998-03-25 | |||
| CN101933096A | 2010-12-29 | |||
| CN1420566A | 2003-05-28 | |||
| CN101866941A | 2010-10-20 | |||
| US8681556B2 | 2014-03-25 |
Attorney, Agent or Firm:
CHINA SCIENCE PATENT & TRADEMARK AGENT LTD. (CN)
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