Title:
MEMORY CIRCUIT DEVICE AND METHOD FOR USING SAME
Document Type and Number:
WIPO Patent Application WO/2019/054495
Kind Code:
A1
Abstract:
The purpose of the present invention is to provide a memory circuit device that enables the circuit to be downscaled. The memory circuit device is provided with: multiple memory cells 11, each comprising a variable resistance memory component; a write circuit unit 20 for writing data into the memory cells; and a read circuit unit 30 for reading the data written in the memory cells. The device is configured to have: a selection circuit unit 40 which is disposed in common for the write circuit unit 20 and read circuit unit 30 and selects a memory cell to be activated out of the multiple memory cells 11 on the basis of cell designation information; and control circuit parts 14a, 14b, 15 which selectively enables either the write circuit unit 20 to write data into the memory cell selected by the selection circuit unit 40 or the read circuit unit 30 to read data therefrom.
Inventors:
HANYU TAKAHIRO (JP)
SUZUKI DAISUKE (JP)
OHNO HIDEO (JP)
ENDOH TETSUO (JP)
SUZUKI DAISUKE (JP)
OHNO HIDEO (JP)
ENDOH TETSUO (JP)
Application Number:
PCT/JP2018/034229
Publication Date:
March 21, 2019
Filing Date:
September 14, 2018
Export Citation:
Assignee:
UNIV TOHOKU (JP)
International Classes:
G11C11/16; G06F5/10; G06F12/00; G11C8/10; H03K19/177
Foreign References:
| JPH0273591A | 1990-03-13 | |||
| JP2013013059A | 2013-01-17 | |||
| JP2017059679A | 2017-03-23 | |||
| JPS61269288A | 1986-11-28 | |||
| JP2000011637A | 2000-01-14 | |||
| JP2010081172A | 2010-04-08 |
Attorney, Agent or Firm:
EICHI PATENT & TRADEMARK CORP. (JP)
Download PDF: