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Title:
MEMORY CIRCUIT, DRIVE METHOD FOR SAME, NONVOLATILE STORAGE DEVICE USING SAME, AND LIQUID CRYSTAL DISPLAY DEVICE
Document Type and Number:
WIPO Patent Application WO/2013/080784
Kind Code:
A1
Abstract:
Provided is a memory circuit provided with memory elements to which writing is possible with low current and low voltage, in other words, low power consumption, and also provided is a nonvolatile storage device, for which chip size can easily be made small, using the same. A memory element (1) is a memory transistor provided with a transistor structure having: a source electrode (14); a drain electrode (15); a gate electrode (11); a source region constituted of a metal oxide semiconductor layer (13); a drain region; and a channel region. By making a write current with a current density of a prescribed value or greater flow in the channel region, the resistance characteristics between the source and drain are reduced in resistance by joule heat that is generated, and changed to ohmic resistance characteristics regardless of the voltage application state for the gate electrode. Information is stored during a state exhibiting ohmic resistance characteristics after writing and a state exhibiting current and voltage characteristics for a transistor dependent on the voltage application state to the gate electrode prior to writing.

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Inventors:
UEDA NAOKI
Application Number:
PCT/JP2012/079249
Publication Date:
June 06, 2013
Filing Date:
November 12, 2012
Export Citation:
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Assignee:
SHARP KK (JP)
UEDA NAOKI
International Classes:
H01L21/8246; G02F1/133; G02F1/1368; H01L21/8244; H01L27/10; H01L27/105; H01L27/11; H01L27/112; H01L29/786
Domestic Patent References:
WO2009028426A12009-03-05
WO2010074689A12010-07-01
Foreign References:
JP2011233551A2011-11-17
JP2008306157A2008-12-18
JP2011171771A2011-09-01
JPH0198198A1989-04-17
JP2002511631A2002-04-16
Attorney, Agent or Firm:
MASAKI YOSHIFUMI (JP)
Yoshifumi Masaki (JP)
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