Title:
MEMORY CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2023/089778
Kind Code:
A1
Abstract:
A memory circuit that has: a plurality of memory groups that execute a write operation or a read operation in response to a request signal; a plurality of memory group control units that are provided corresponding to each of the plurality of memory groups; and a first memory control unit that outputs a request signal to an adjacent memory group control unit. Each memory group control unit outputs to a memory group corresponding to the request signal or to a later-stage memory group control unit, according to an address signal included in the received request signal. As a result, each of the memory group control units can control access for each memory group and increase in power consumption can be suppressed while still suppressing increase in access time.
Inventors:
OTSUKA TATSUSHI (JP)
Application Number:
PCT/JP2021/042634
Publication Date:
May 25, 2023
Filing Date:
November 19, 2021
Export Citation:
Assignee:
SOCIONEXT INC (JP)
International Classes:
G11C7/10; G11C5/14
Foreign References:
| JP2006065697A | 2006-03-09 |
Attorney, Agent or Firm:
ITOH, Tadashige et al. (JP)
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