Title:
MEMORY CONTROL DEVICE AND MEMORY CONTROL METHOD
Document Type and Number:
WIPO Patent Application WO/2017/179176
Kind Code:
A1
Abstract:
Provided is a memory control device which controls writing of data to a memory device which is provided with a block access function, said device comprising a plurality of sort buffers which, when array data is being written to the memory device, sort the array data. The array data which has been sorted by the sort buffers is written to the memory device using the block access function. It is thus possible to further accelerate the writing of array data.
Inventors:
TAMIYA YUTAKA (JP)
Application Number:
PCT/JP2016/062025
Publication Date:
October 19, 2017
Filing Date:
April 14, 2016
Export Citation:
Assignee:
FUJITSU LTD (JP)
International Classes:
G06F12/02; G06F17/16
Foreign References:
| JPH05342098A | 1993-12-24 | |||
| JPH04278651A | 1992-10-05 |
Other References:
KIYOSHI KUMAHATA: "Performance Tuning for Gradient Kernel of the FrontFlow/blue on the K computer", IPSJ TRANSACTIONS ON ADVANCED COMPUTING SYSTEMS, vol. 6, no. 3, 30 September 2013 (2013-09-30), pages 31 - 42
Attorney, Agent or Firm:
AOKI, Atsushi et al. (JP)
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