Title:
MEMORY CONTROL DEVICE
Document Type and Number:
WIPO Patent Application WO/2023/189358
Kind Code:
A1
Abstract:
A memory control device according to one embodiment of the present disclosure comprises a detection unit and a conversion unit. In a plurality of memory access requests relating to accepted memory access, the detection unit detects either switching between a read bank group interleave and a write request or switching between a write bank group interleave and a read request. The conversion unit converts the BL length of the memory access request included in the read bank group interleave or the write bank group interleave on the basis of the number of memory access requests in the read bank group interleave or write bank group interleave and timing information pertaining to a command corresponding to an immediately preceding memory access request in the read bank group interleave or write bank group interleave.
Inventors:
IKEZOE TAKEHARU (JP)
IKARASHI TAKAHIRO (JP)
IKARASHI TAKAHIRO (JP)
Application Number:
PCT/JP2023/009080
Publication Date:
October 05, 2023
Filing Date:
March 09, 2023
Export Citation:
Assignee:
SONY SEMICONDUCTOR SOLUTIONS CORP (JP)
International Classes:
G06F12/02; G06F12/06
Domestic Patent References:
| WO2016185879A1 | 2016-11-24 |
Foreign References:
| US20160378366A1 | 2016-12-29 | |||
| JP2020187747A | 2020-11-19 | |||
| JP2001135079A | 2001-05-18 |
Attorney, Agent or Firm:
TSUBASA PATENT PROFESSIONAL CORPORATION (JP)
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