MEMORY CONTROL METHOD AND DEVICE

WIPO Patent Application WO/2018/157569

A1

A memory control method and device, for use in reducing wiring difficulty and improving signal quality when controlling SDRAMs belonging to one RANK to execute an access instruction. The method comprises: generating an access instruction for two SDRAMs according to instruction requirements (S601), the two SDRAMs being fixed to two sides of a single board in a mirrored manner; generating two chip select signals according to the access instruction (S602), a first chip select signal in the two chip select signals being used for enabling a first SDRAM in the two SDRAMs, and a second chip select signal in the two chip select signals being used for enabling a second SDRAM in the two SDRAMs; making at least one chip select signal in the two chip select signals valid according to mode parameters (S603), the mode parameters being used for indicating the validity of each chip select signal in the two chip select signals; and outputting the access instruction and the first chip select signal to the first SDRAM, and outputting the access instruction and the second chip select signal to the second SDRAM (S604).

WO/2021/011200	UNMAP FOR COARSE MAPPING MEMORY SUB-SYSTEM
WO/2009/067386	BIDIRECTIONAL MEMORY INTERFACE WITH GLITCH TOLERANT BIT SLICE CIRCUITS

WANG ZENGQIANG (CN)
YANG YIFENG (CN)

PCT/CN2017/099101

September 07, 2018

August 25, 2017

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HUAWEI TECH CO LTD (CN)

G06F13/16

CN105095122A	2015-11-25
CN102077180A	2011-05-25
CN104461956A	2015-03-25
CN101118523A	2008-02-06
US20100232197A1	2010-09-16

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