MEMORY CONTROL METHOD AND SYSTEM

Title:

MEMORY CONTROL METHOD AND SYSTEM

Document Type and Number:

WIPO Patent Application WO/2012/101760

Kind Code:

A1

Abstract:

In order to avoid memory access competition by multiple devices, the multicore processor system (100) for time t3 represented by the notation '103' assigns processes to be executed by an application #0 to a GPU (106), and assigns processes to be executed by an application #1 to a CPU (#0). Next, the multicore processor system (100) controls a memory controller (112) in such a manner that the GPU (106) accesses a memory area for application #0 (115#0), via a port for application #0 (113#0). Furthermore, the multicore processor system (100) controls a memory controller (112) in such a manner that the CPU (#0) accesses a memory area for application #1 (115#1) via a port 113#1, which is not the port for application #0.

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Inventors:

YAMAUCHI HIROMASA (JP)
YAMASHITA KOICHIRO (JP)
SUZUKI TAKAHISA (JP)
KURIHARA KOJI (JP)
OTOMO TOSHIYA (JP)

Application Number:

PCT/JP2011/051354

Publication Date:

August 02, 2012

Filing Date:

January 25, 2011

Export Citation:

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Assignee:

FUJITSU LTD (JP)
YAMAUCHI HIROMASA (JP)
YAMASHITA KOICHIRO (JP)
SUZUKI TAKAHISA (JP)
KURIHARA KOJI (JP)
OTOMO TOSHIYA (JP)

International Classes:

G06F12/00; G06F9/50

Foreign References:

JP2006350622A	2006-12-28
JP2010152733A	2010-07-08
JP2010097311A	2010-04-30

Other References: