Title:
MEMORY CONTROLLER AND MEMORY ACCESS SYSTEM
Document Type and Number:
WIPO Patent Application WO/2012/011216
Kind Code:
A1
Abstract:
A controller unit (20) outputs a first signal (DQS) and a second signal (DATA) which maintains a phase relationship with the first signal. The second signal (DATA) is input through a FIFO memory (110) of an error detection unit (10) to a memory I/F unit (30). The memory I/F unit (30) performs timing adjustment of the first and second signals (DQS, DATA), outputs to a memory (5), and performs loop-back of the second signal (DATA). A data comparator (125) compares the loop-backed second signal (DATA) with the original second signal (DATA) output from the FIFO memory (110) and corresponding to the loop-backed signal.
Inventors:
NAKABAYASHI, Hisataka (())
仲林久貴 (())
TAKEDA, Miho (())
仲林久貴 (())
TAKEDA, Miho (())
Application Number:
JP2011/002480
Publication Date:
January 26, 2012
Filing Date:
April 27, 2011
Export Citation:
Assignee:
PANASONIC CORPORATION (1006, Oaza Kadoma Kadoma-sh, Osaka 01, 〒5718501, JP)
パナソニック株式会社 (〒01 大阪府門真市大字門真１００６番地 Osaka, 〒5718501, JP)
NAKABAYASHI, Hisataka (())
仲林久貴 (())
パナソニック株式会社 (〒01 大阪府門真市大字門真１００６番地 Osaka, 〒5718501, JP)
NAKABAYASHI, Hisataka (())
仲林久貴 (())
International Classes:
G06F12/00
Attorney, Agent or Firm:
MAEDA, Hiroshi et al. (Osaka-Marubeni Bldg, 5-7Hommachi 2-chome, Chuo-ku, Osaka-sh, Osaka 53, 〒5410053, JP)
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Claims: