Title:
MEMORY CONTROLLER, MEMORY CONTROL METHOD, AND SEMICONDUCTOR STORAGE DEVICE
Document Type and Number:
WIPO Patent Application WO/2017/046958
Kind Code:
A1
Abstract:
Provided is a memory controller, which transmits commands, addresses, and data over identical bus signal lines to each of a plurality of memory devices, and in which, in order to transmit an identification signal for identifying the commands, addresses, and data in the bus signal line over a common memory signal line which is shared among the plurality of memory devices, the signal is positioned upon the signal line. When data is indicated by the identification signal and the data is being transferred over the bus signal line to a first memory device, the memory controller interrupts the transfer of the data to the first memory device, indicates a command with the identification signal, issues a command to the second memory device, indicates an address with the identification signal, and issues an address to the second memory device.
Inventors:
IKEDA YASUHIRO (JP)
UEMATSU YUTAKA (JP)
OSHIMI MASATSUGU (JP)
UEMATSU YUTAKA (JP)
OSHIMI MASATSUGU (JP)
Application Number:
PCT/JP2015/076775
Publication Date:
March 23, 2017
Filing Date:
September 18, 2015
Export Citation:
Assignee:
HITACHI LTD (JP)
International Classes:
G06F13/16
Foreign References:
| JP2003131940A | 2003-05-09 | |||
| JP2007164787A | 2007-06-28 | |||
| JP2013520721A | 2013-06-06 |
Attorney, Agent or Firm:
WILLFORT INTERNATIONAL PATENT FIRM (JP)
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