Title:
MEMORY CONTROLLER AND MEMORY DEVICE
Document Type and Number:
WIPO Patent Application WO/2023/181892
Kind Code:
A1
Abstract:
A memory controller according to one aspect of the present disclosure controls a read operation for a nonvolatile memory cell array unit, and includes a detection unit and a control unit. The detection unit detects the number of bits in which information corresponding to a high resistance state is erroneously read as information corresponding to a low resistance state, on the basis of first data with an error correction code read from a plurality of first memory cells that are part of a plurality of memory cells, and second data obtained by performing error correction using an error correction code on the first data. The control unit determines whether or not to change read voltages applied to the plurality of first memory cells, on the basis of the number of bits detected by the detection unit.
Inventors:
OKUBO HIDEAKI (JP)
NAKANISHI KENICHI (JP)
NAKANISHI KENICHI (JP)
Application Number:
PCT/JP2023/008414
Publication Date:
September 28, 2023
Filing Date:
March 06, 2023
Export Citation:
Assignee:
SONY SEMICONDUCTOR SOLUTIONS CORP (JP)
International Classes:
G06F11/10; G06F12/00; G06F12/02; G11C13/00
Foreign References:
| JP2018163720A | 2018-10-18 | |||
| JP2012221536A | 2012-11-12 | |||
| JP2018160065A | 2018-10-11 | |||
| JP2012256392A | 2012-12-27 |
Attorney, Agent or Firm:
TSUBASA PATENT PROFESSIONAL CORPORATION (JP)
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