Title:
MEMORY CONTROLLER, MEMORY SYSTEM, INFORMATION SYSTEM AND MEMORY CONTROL METHOD
Document Type and Number:
WIPO Patent Application WO/2018/051647
Kind Code:
A1
Abstract:
The present invention suppresses a delay due to a retry process for the occurrence of a memory write error. A subregion command holding unit holds a host command, as a subregion command, that is decomposed for each subregion to be accessed. A subregion address conversion unit translates, for a subregion command, the address of a subregion to be accessed into a memory address. A subregion command execution unit executes the address-translated subregion command and accesses memory. When a write error occurs in memory with regard to the subregion command, an address translation management unit executes a process of preparing an alternative region for the subregion command that caused the write error in parallel to the execution of other subregion commands by the subregion command execution unit.
Inventors:
NAKANISHI KENICHI (JP)
Application Number:
PCT/JP2017/027150
Publication Date:
March 22, 2018
Filing Date:
July 27, 2017
Export Citation:
Assignee:
SONY CORP (JP)
International Classes:
G06F12/16; G06F11/20; G06F12/00
Foreign References:
| JP2011180831A | 2011-09-15 | |||
| JP2015043183A | 2015-03-05 |
Attorney, Agent or Firm:
MARUSHIMA, Toshikazu (JP)
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