Title:
MEMORY CONTROLLER, MEMORY SYSTEM, AND INFORMATION PROCESSING SYSTEM
Document Type and Number:
WIPO Patent Application WO/2017/018013
Kind Code:
A1
Abstract:
The present invention eliminates a delay/overhead in a memory device. A command reception unit receives a read command for requesting reading of data from the memory device. In accordance with a state of the memory device, a control unit selects either a first mode, in which on completion of a preceding request, a read request is issued to the memory device to read data from a memory cell array of the memory device and to output the read data, or a second mode, in which when a predetermined time has elapsed after a sense request for reading of data from the memory cell array is issued, a data-out request is issued to the memory device to output the data read in response to the sense request. A request issuance unit issues relevant requests to the memory device in accordance with the first or second mode as selected by the control unit.
Inventors:
TERADA HARUHIKO (JP)
Application Number:
PCT/JP2016/063222
Publication Date:
February 02, 2017
Filing Date:
April 27, 2016
Export Citation:
Assignee:
SONY CORP (JP)
International Classes:
G06F12/00; G11C13/00
Foreign References:
| JP2009503726A | 2009-01-29 | |||
| JP2002259322A | 2002-09-13 |
Attorney, Agent or Firm:
MARUSHIMA, Toshikazu (JP)
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