Title:
MEMORY CONTROLLER
Document Type and Number:
WIPO Patent Application WO/2016/153005
Kind Code:
A1
Abstract:
The present invention suppresses noise generated when data are transferred to a memory. The memory controller (C) is provided with: a write unit (6) for writing transmission data into a memory; and a read unit (7) for reading the data from the memory. The write unit (6) is provided with a substitution unit (6b) which, if the pattern of "1s" and "0s" arranged in a bit string constituting the data to be transmitted to a signal line (DL) is a preset target pattern to be substituted, substitutes this bit string with a substitute bit string, with which noise can be suppressed, before writing the data to the memory. The read unit (7) is provided with a restoration unit (7b) for restoring the initial bit string from the substitute bit string read from the memory.
Inventors:
NARUSE TAKANOBU (JP)
Application Number:
PCT/JP2016/059472
Publication Date:
September 29, 2016
Filing Date:
March 24, 2016
Export Citation:
Assignee:
AISIN AW CO (JP)
International Classes:
G06F11/00; H03M5/14; H04L25/49
Domestic Patent References:
| WO2012120813A1 | 2012-09-13 |
Foreign References:
| JP2008102705A | 2008-05-01 |
Other References:
See also references of EP 3242211A4
Attorney, Agent or Firm:
R&C IP LAW FIRM (JP)
Patent business corporation R&C (JP)
Patent business corporation R&C (JP)
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