Title:
MEMORY DEVICE CAPABLE OF DYNAMICALLY SWITCHING ERROR CORRECTION AND ERROR DETECTION IN ON-DIE ERROR CORRECTION CODE
Document Type and Number:
WIPO Patent Application WO/2023/101097
Kind Code:
A1
Abstract:
The present invention relates to a memory device, which dynamically switches error correction and error detection so that error correction and error detection can be selected according to circumstances. The present invention comprises: an error correction code encoder comprising a parity generation unit, which generates parity bits from data bits input from a memory control unit, so as to write, on a memory cell array, a codeword including the data bits and the parity bits; and an error correction code decoder comprising a syndrome generation unit, which reads the codeword including the data bits and the parity bits written on the cell array, and then computes the codeword to generate syndrome data, a syndrome decoding unit, which decodes the syndrome data generated by the syndrome generation unit so as to generate error location bits indicating the location of an error bit, an error correction unit, which generates correction bit data by comparing and computing respective bits per location of the data bits and the error location bits if the data bits from the memory cell array and the error location bits generated by the syndrome decoding unit are received, an error detection unit, which receives the syndrome data output from the syndrome generation unit, and then performs an OR calculation and outputs a digital signal "1" or a digital signal "0" as an calculation value, a PIM enable unit, which includes the digital signal "0" and the digital signal "1" so as to output either the digital signal "0' or the digital signal "1" while controlled by means of the memory control unit, and a PIM enable switch unit, which receives the data bits from the memory cell array, receives the correction bit data from the error correction unit, receives either the digital signal "0" or the digital signal "1" from the PIM enable unit so as to output the correction bit data output from the error correction unit if the digital signal "0" is received from the PIM enable unit and output the data bits if the digital signal "1" is received from the PIM enable unit.
Inventors:
AHN JUNG HO (KR)
PARK JAE HYUN (KR)
YUN SUNG MIN (KR)
PARK JAE HYUN (KR)
YUN SUNG MIN (KR)
Application Number:
PCT/KR2021/019871
Publication Date:
June 08, 2023
Filing Date:
December 24, 2021
Export Citation:
Assignee:
SEOUL NAT UNIV R&DB FOUNDATION (KR)
International Classes:
G06F11/10; G06F9/30; G06F15/78; G11C29/42; G11C29/52
Foreign References:
| KR20130004045A | 2013-01-09 | |||
| KR20200133808A | 2020-11-30 | |||
| KR20200142213A | 2020-12-22 | |||
| KR20210092391A | 2021-07-26 | |||
| JP2006179131A | 2006-07-06 |
Attorney, Agent or Firm:
OH, Young Kyun (KR)
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