Title:
MEMORY DEVICE AND MEMORY DEVICE CONTROL METHOD
Document Type and Number:
WIPO Patent Application WO/2018/212082
Kind Code:
A1
Abstract:
A memory device according to one embodiment comprises a memory cell. The memory cell includes: a variable resistance element the resistance state of which changes between a first resistance state and a second resistance state; and a selection element. The memory device is further provided with a drive circuit that writes data to and erases data from the memory cell by changing the state of the variable resistance element. When erasing data, the drive circuit changes, in a stepwise manner, the voltage applied to the memory cell and changes, in a stepwise manner, a current limit value that limits the size of the current flowing to the memory cell.
Inventors:
MORI YOTARO (JP)
KITAGAWA MAKOTO (JP)
OKUNO JUN (JP)
TERADA HARUHIKO (JP)
KITAGAWA MAKOTO (JP)
OKUNO JUN (JP)
TERADA HARUHIKO (JP)
Application Number:
PCT/JP2018/018251
Publication Date:
November 22, 2018
Filing Date:
May 11, 2018
Export Citation:
Assignee:
SONY SEMICONDUCTOR SOLUTIONS CORP (JP)
International Classes:
G11C13/00
Domestic Patent References:
| WO2016072173A1 | 2016-05-12 |
Foreign References:
| JP2014075170A | 2014-04-24 | |||
| JP2010211895A | 2010-09-24 |
Attorney, Agent or Firm:
TSUBASA PATENT PROFESSIONAL CORPORATION (JP)
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