Title:
MEMORY DEVICE AND MANUFACTURING METHOD THEREFOR
Document Type and Number:
WIPO Patent Application WO/2011/080866
Kind Code:
A1
Abstract:
Disclosed is a memory device provided with a plurality of memory cells and an output line (12) shared among the memory cells. Each memory cell is provided with a transistor (6) formed on a substrate (1) and a resistance-change element (10) that has a lower electrode (7), an upper electrode (9) that contains a noble metal, and a resistance-change layer (8) sandwiched between the lower electrode (7) and the upper electrode (9). The resistance of the resistance-change layer (8) changes reversibly due to electric pulses that go through the transistor (6) and are applied between the lower electrode (7) and the upper electrode (9). The output line (12) is directly connected to the upper electrodes (9) of the memory cells.
Inventors:
ARITA KOJI
MIKAWA TAKUMI
MIKAWA TAKUMI
Application Number:
PCT/JP2010/006738
Publication Date:
July 07, 2011
Filing Date:
November 17, 2010
Export Citation:
Assignee:
PANASONIC CORP (JP)
ARITA KOJI
MIKAWA TAKUMI
ARITA KOJI
MIKAWA TAKUMI
International Classes:
H01L27/105; H01L27/10; H01L45/00; H01L49/00
Foreign References:
| JP2009124167A | 2009-06-04 | |||
| JP2009289822A | 2009-12-10 | |||
| JP2004363604A | 2004-12-24 | |||
| JP2007501520A | 2007-01-25 |
Attorney, Agent or Firm:
NII, Hiromori (JP)
New house Extensive 守 (JP)
New house Extensive 守 (JP)
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