MEMORY DEVICE AND MANUFACTURING METHOD THEREOF, AND ELECTRONIC DEVICE COMPRISING THE MEMORY DEVICE

WIPO Patent Application WO/2018/058926

A1

Provided are a memory device and a manufacturing method thereof, and an electronic device comprising the memory device. The memory device comprises multiple memory cell layers sequentially stacked on a substrate (1001). Each memory cell layer comprises a first array of first memory cells and a second array of second memory cells. The first array and the second array are mutually nested. The first memory cells and the second memory cells in the respective memory cell layers are substantially aligned with each other in a direction in which the memory cell layers are stacked. Each first memory cell is a vertical device comprising a first source/drain layer (1003), channel layers (1005, 1009), and a second source/drain layer (1007) sequentially stacked. Each second memory cell is a vertical device in an active semiconductor layer (1109) extending in a stack direction. Each first memory cell and each second memory cell comprise respective memory gate stacks, and the memory gate stacks have a common gate conductor layer (1025). The gate conductor layers (1025) at the same memory cell layer are integrally formed.

ZHU HUILONG (US)

PCT/CN2017/078972

April 05, 2018

March 31, 2017

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INST OF MICROELECTRONICS CAS (CN)

H01L27/11568; H01L27/11521; H01L27/11507

CN106340521A	2017-01-18
CN106298679A	2017-01-04
CN106206600A	2016-12-07
CN106158877A	2016-11-23
CN104022120A	2014-09-03
CN105304633A	2016-02-03
US20160013127A1	2016-01-14

CHINA SCIENCE PATENT & TRADEMARK AGENT LTD. (CN)

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