Title:
MEMORY DEVICE AND METHOD OF CONTROLLING CPU
Document Type and Number:
WIPO Patent Application WO/2012/011222
Kind Code:
A1
Abstract:
A memory (102) is provided with a storage unit (106b) for storing the number of times a rewriting voltage pulse is applied to a memory array and a required time outputting unit (106b) for outputting data representing the required time for the rewriting operation on the basis of the application number stored in the storage unit (106b).
Inventors:
NISHIKAWA, Kazuyo (())
西川 和予 (())
NOICHI, Shuuhei (())
乃一 修平 (())
ARITA, Makoto (())
西川 和予 (())
NOICHI, Shuuhei (())
乃一 修平 (())
ARITA, Makoto (())
Application Number:
JP2011/003445
Publication Date:
January 26, 2012
Filing Date:
June 16, 2011
Export Citation:
Assignee:
PANASONIC CORPORATION (1006, Oaza Kadoma Kadoma-sh, Osaka 01, 〒5718501, JP)
パナソニック株式会社 (〒01 大阪府門真市大字門真１００６番地 Osaka, 〒5718501, JP)
NISHIKAWA, Kazuyo (())
西川 和予 (())
NOICHI, Shuuhei (())
乃一 修平 (())
パナソニック株式会社 (〒01 大阪府門真市大字門真１００６番地 Osaka, 〒5718501, JP)
NISHIKAWA, Kazuyo (())
西川 和予 (())
NOICHI, Shuuhei (())
乃一 修平 (())
International Classes:
G11C16/02; G06F12/06; G06F12/16; G11C16/06
Attorney, Agent or Firm:
MAEDA, Hiroshi et al. (Osaka-Marubeni Bldg, 5-7Hommachi 2-chome, Chuo-ku, Osaka-sh, Osaka 53, 〒5410053, JP)
Claims:
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